Specifications

Cortex-M3 / Cortex-M3 with ETM (AT420/AT425)
Date of Issue: 12-Nov-2008 ARM Errata Notice Document Revision 2.0
PR326-PRDC-009450 v2.0
© Copyright ARM Limited 2008. All rights reserved. Page 4 of 20
Non Confidential
Contents
INTRODUCTION 5
ERRATA SUMMARY TABLE 7
ERRATA PRESENT ON RELEASE R2P0-00REL0 8
563915: Event Register is not set by interrupts and debug 8
602117: LDRD with base in list may result in incorrect base register when interrupted or
faulted 9
ERRATA FIXED ON RELEASE R2P0-00REL0 11
531064: SWJ-DP missing POR reset sync 11
511864: Cortex-M3 may fetch instructions using incorrect privilege on return from an
exception 12
532314: DWT CPI counter increments during sleep 13
538714: Cortex-M3 TPIU Clock Domain crossing 14
548721: Internal write buffer could be active whilst asleep 15
463763: BKPT in debug monitor mode can cause DFSR mismatch 16
463764: Core may freeze for SLEEPONEXIT single instruction ISR 17
463769: Unaligned MPU fault during a write may cause the wrong data to be written to a
successful first access 18
ERRATA FIXED ON RELEASE R1P1-01REL0 19
429964: Async not generated if no trace in previous session 19
429965: Trigger packets sometimes not inserted in trace stream 20