Specifications

Cortex-M3 / Cortex-M3 with ETM (AT420/AT425)
Date of Issue: 12-Nov-2008 ARM Errata Notice Document Revision 2.0
PR326-PRDC-009450 v2.0
© Copyright ARM Limited 2008. All rights reserved. Page 7 of 20
Non Confidential
Errata Summary Table
The errata associated with this product affect product versions as below.
A cell shown thus X indicates that the defect affects the revision shown at the top of that column.
ID Cat Summary of Erratum
r1p1-00rel0 r1p1-01rel0 r2p0-00rel0
602117 Cat 2 LDRD with base in list may result in incorrect base register when
interrupted or faulted
X X X
563915 Cat 2 Event Register is not set by interrupts and debug X X X
531064 Impl SWJ-DP missing POR reset sync X X
511864 Cat 3 Cortex-M3 may fetch instructions using incorrect privilege on return from
an exception
X X
532314 Cat 3 DWT CPI counter increments during sleep X X
538714 Cat 3 Cortex-M3 TPIU Clock Domain crossing X X
548721 Cat 3 Internal write buffer could be active whilst asleep X X
463763 Cat 3 BKPT in debug monitor mode can cause DFSR mismatch X X
463764 Cat 3 Core may freeze for SLEEPONEXIT single instruction ISR X X
463769 Cat 3 Unaligned MPU fault during a write may cause the wrong data to be
written to a successful first access
X X
429964 Cat 2 Async not generated if no trace in previous session X
429965 Cat 2 Trigger packets sometimes not inserted in trace stream X