Specifications

Cortex-M3 / Cortex-M3 with ETM (AT420/AT425)

Date of Issue: 12-Nov-2008 ARM Errata Notice Document Revision 2.0

PR326-PRDC-009450 v2.0

Non Confidential

Errata present on release r2p0-00rel0

563915: Event Register is not set by interrupts and debug

Status

Affects: product Cortex-M3, Cortex-M3 with ETM.

Fault status: Cat 2, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0,r2p0-00rel0, Open.

Description

The event register used for WFE wake-up events should be set for the following conditions:

1. Event communication (including SEV on local processor)

2. Any exception entering pending state when SEVONPEND is set

3. Exception entry

4. Exception exit

5. Debug event when debug is enabled

In r0p0, r1p0, r1p1 and r2p0 versions of Cortex-M3 the event register is not set for the exception entry,

exception exit or debug events.

Conditions

1. An interrupt or debug event occurs whilst the internal event register is clear and the core is not sleeping

2. A WFE is executed

3. No further interrupts or events occur

Implications

If interrupts related to a WFE sleep can be generated before the WFE is executed then it may be possible for

the event to be missed. The interrupt will occur and the handler will be executed for that interrupt but the event

interrupts occur.

Workaround

An implementation time workaround is to connect up the missing events to the RXEV input of Cortex-M3. This

can be achieved by decoding interrupt events using ETMINTSTAT as well as using the HALTED output. RXEV

needs to be asserted whenever ETMINTSTAT is equal to 3'b001 or 3'b010 or when HALTED is asserted. Since

ETMINTSTAT is part of the ETM interface the ETM interface needs to be enabled for this workaround. This is

achieved by asserting the ETMPWRUP input on Cortex-M3.

A software workaround is to insert the SEV instruction at the beginning and end of all exception handlers.