User guide

Embedded Trace Macrocell
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 10-15
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10.3.5 System Configuration Register, ETMSCR
The ETMSCR characteristics are:
Purpose Shows the ETM features supported by the implementation of the ETM
macrocell.
Usage constraints There are no usage constraints.
Configurations This register is only available if the processor is configured to use the
ETM.
Attributes See the register summary in Table 10-6 on page 10-9.
Figure 10-4 shows the ETMSCR bit assignments.
Figure 10-4 ETMSCR bit assignments
Table 10-9 shows the ETMSCR bit assignments.
[15:13] Number of counters The value of these bits is 0b001 , indicating that one counter is implemented.
[12:8] Number of memory map decoders The value of these bits is
0b00000 , indicating that memory map decoder inputs are
not implemented.
[7:4] Number of data value comparators The value of these bits is
0b0000 , indicating that data value comparators are not
implemented.
[3:0] Number of address comparator pairs The value of these bits is
0b0000 , indicating that address comparator pairs are not
implemented.
Table 10-8 ETMCCR bit assignments (continued)
Bits Name Function
No fetch comparisons
Maximum
port size[2:0]
31 17 16 15 12 8 7 4 3 0
Reserved
18 14 11 10 9 2
Reserved,
reads as 1
Reserved,
reads as 0x0
Reserved
(N -1), where N = Number of supported processors
Port mode supported
Port size supported
Maximum port size[3]
FIFOFULL supported
Table 10-9 ETMSCR bit assignments
Bits Name Function
[31:18] - Reserved.
[17] No Fetch comparisons The value of this bit is 1, indicating that fetch comparisons are not implemented.
[16:15] - Reserved.
[14:12] (N-1) These bits give the number of supported processors minus 1. The value of these bits is
0b000 ,
indicating that there is only one processor connected.
[11] Port mode supported This bit reads as 1 if the currently selected port mode is supported. This has no effect on the
TPIU trace port.