User guide

Revisions
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. A-6
ID072410 Non-Confidential
Descriptions of the memory system and of exceptions moved to
Chapter 3.
Chapter 3 Programmers Model
Component-specific registers moved from System Control
chapter to appropriate chapters within the manual.
Chapter 4 System Control
Deleted Clocking and Resets chapter. See the implementation documentation for the
processor.
Deleted Power Management chapter.
In the Memory Protection Unit and Nested Vector Interrupt
Controller chapters, removed description of
architecturally-defined registers.
Reorganized debug description into a single chapter. Chapter 7 Debug
Deleted Bus Interface chapter and moved high-level information
to appropriate chapters.
Chapter 1 Introduction
Chapter 2 Functional Description
Chapter 3 Programmers Model
Deleted Debug Port chapter and incorporated general information
from this chapter into chapters 2 and 7.
Chapter 2 Functional Description
Chapter 7 Debug
Moved information from the System Debug chapter to create new
chapters for the Data Watchpoint and Trace Unit and the
Instrumentation Trace Macrocell Unit.
Chapter 8 Data Watchpoint and Trace Unit
Chapter 9 Instrumentation Trace Macrocell Unit
Reorganized Embedded Trace Macrocell description into a single
chapter.
Chapter 10 Embedded Trace Macrocell
Removed signal information and architecturally-defined register
descriptions from the Trace Port Interface Unit chapter.
Removed duplicate information. See the ARMv7-M
Architecture Reference Manual and the
implementation documentation for the processor.
Moved instruction timing information to chapter 3. Instruction set summary on page 3-4
Removed AC Characteristics and Signal Descriptions chapters. See the implementation documentation for the
processor.
Table A-4 Differences between issue H and issue I
Change Location
Updated Bus interfaces information. Bus interfaces on page 2-4
Added informaion on Private Peripheral Bus Private Peripheral Bus (PPB) on page 2-5
Updated Load/store timings information. Load/store timings on page 3-8
Updated Exclusive monitor information. Exclusive monitor on page 3-15
Updated Reset values for Register summary information. Table 4-1 on page 4-3
Reset values updated. Table 4-1 on page 4-3
Updated Reset values for MPU register information. Table 5-1 on page 5-4
Changed address range of NVIC_IPR registers. Table 6-1 on page 6-4
Updated values for the Cortex-M3 ROM table information and added
Peripheral IDs 5-7.
Table 7-1 on page 7-3
Table A-3 Differences between issue G and issue H (continued)
Change Location