User guide

Glossary
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. Glossary-4
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Byte An 8-bit data item.
Byte-invariant In a byte-invariant system, the address of each byte of memory remains unchanged when
switching between little-endian and big-endian operation. When a data item larger than a byte
is loaded from or stored to memory, the bytes making up that data item are arranged into the
correct order depending on the endianness of the memory access. The ARM architecture
supports byte-invariant systems in ARMv6 and later versions. When byte-invariant support is
selected, unaligned halfword and word memory accesses are also supported. Multi-word
accesses are expected to be word-aligned.
See also Word-invariant.
Clock gating Gating a clock signal for a macrocell with a control signal and using the modified clock that
results to control the operating state of the macrocell.
Clocks Per Instruction (CPI)
See Cycles Per Instruction (CPI).
Cold reset Also known as power-on reset.
See also Warm reset.
Context The environment that each process operates in for a multitasking operating system.
See also Fast context switch.
Core A core is that part of a processor that contains the ALU, the datapath, the general-purpose
registers, the Program Counter, and the instruction decode and control circuitry.
Core reset See Warm reset.
CoreSight The infrastructure for monitoring, tracing, and debugging a complete system on chip.
CPI See Cycles per instruction.
Cycles Per instruction (CPI)
Cycles per instruction (or clocks per instruction) is a measure of the number of computer
instructions that can be performed in one clock cycle. This figure of merit can be used to
compare the performance of different CPUs that implement the same instruction set against each
other. The lower the value, the better the performance.
Data Abort An indication from a memory system to the core of an attempt to access an illegal data memory
location. An exception must be taken if the processor attempts to use the data that caused the
abort.
See also Abort.
DCode Memory Memory space at 0x00000000 to 0x1FFFFFFFF .
Debug Access Port (DAP)
A TAP block that acts as an AMBA, AHB or AHB-Lite, master for access to a system bus. The
DAP is the term used to encompass a set of modular blocks that support system wide debug. The
DAP is a modular component, intended to be extendable to support optional access to multiple
systems such as memory mapped AHB and CoreSight APB through a single debug interface.
Debugger A debugging system that includes a program, used to detect, locate, and correct software faults,
together with custom hardware that supports software debugging.
Embedded Trace Buffer
The ETB provides on-chip storage of trace data using a configurable sized RAM.