User guide

Glossary

ID072410 Non-Confidential

Embedded Trace Macrocell (ETM)

A hardware macrocell that, when connected to a processor core, outputs instruction trace

information on a trace port.

Endianness The scheme that determines the order of successive bytes of a data word when it is stored in

memory.

See also Little-endian and Big-endian

ETB See Embedded Trace Buffer.

ETM See Embedded Trace Macrocell.

Exception An error or event which can cause the processor to suspend the currently executing instruction

stream and execute a specific exception handler or interrupt service routine. The exception could

be an external interrupt or NMI, or it could be a fault or error event that is considered serious

enough to require that program execution is interrupted. Examples include attempting to

perform an invalid memory access, external interrupts, and undefined instructions. When an

exception occurs, normal program flow is interrupted and execution is resumed at the

corresponding exception vector. This contains the first instruction of the interrupt service

routine to deal with the exception.

Exception handler

See Interrupt service routine.

Exception vector See Interrupt vector.

External PPB PPB memory space at

0xE0040000

0xE00FFFFF

Flash Patch and Breakpoint unit (FPB)

A set of address matching tags, that reroute accesses into flash to a special part of SRAM. This

permits patching flash locations for breakpointing and quick fixes or changes.

Formatter The formatter is an internal input block in the ETB and TPIU that embeds the trace source ID

within the data to create a single trace stream.

Halfword A 16-bit data item.

Halt mode One of two mutually exclusive debug modes. In halt mode all processor execution halts when a

breakpoint or watchpoint is encountered. All processor state, coprocessor state, memory and

input/output locations can be examined and altered by the JTAG interface.