User guide

Glossary
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. Glossary-6
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Instruction cycle count
The number of cycles for which an instruction occupies the Execute stage of the pipeline.
Instrumentation trace
A component for debugging real-time systems through a simple memory-mapped trace
interface, providing
printf () style debugging.
Intelligent Energy Management (IEM)
A technology that enables dynamic voltage scaling and clock frequency variation to be used to
reduce power consumption in a device.
Internal PPB PPB memory space at 0xE0000000 to 0xE003FFFF .
Interrupt service
routine
A program that control of the processor is passed to when an interrupt occurs.
Interrupt vector One of a number of fixed addresses in low memory that contains the first instruction of the
corresponding interrupt service routine.
Joint Test Action Group (JTAG)
The name of the organization that developed standard IEEE 1149.1. This standard defines a
boundary-scan architecture used for in-circuit testing of integrated circuit devices. It is
commonly known by the initials JTAG.
JTAG See Joint Test Action Group.
JTAG Debug Port (JTAG-DP)
An optional external interface for the DAP that provides a standard JTAG interface for debug
access.
JTAG-DP See JTAG Debug Port.
LE Little-endian view of memory in both byte-invariant and word-invariant systems. See also
Byte-invariant, Word-invariant.
Little-endian Byte ordering scheme in which bytes of increasing significance in a data word are stored at
increasing addresses in memory.
See also Big-endian and Endianness.
Little-endian memory
Memory in which:
• a byte or halfword at a word-aligned address is the least significant byte or halfword
within the word at that address
• a byte at a halfword-aligned address is the least significant byte within the halfword at that
address.
See also Big-endian memory.
Load/store architecture
A processor architecture where data-processing operations only operate on register contents, not
directly on memory contents.
Load Store Unit (LSU)
The part of a processor that handles load and store transfers.
LSU See Load Store Unit.
Macrocell A complex logic block with a defined interface and behavior. A typical VLSI system comprises
several macrocells (such as a processor, an ETM, and a memory block) plus application-specific
logic.