User guide

Functional Description

ID072410 Non-Confidential

2.2 Interfaces

The processor contains the following external interfaces:

• Bus interfaces

• ETM interface on page 2-6

• AHB Trace Macrocell interface on page 2-6

• Debug Port AHB-AP interface on page 2-6.

2.2.1 Bus interfaces

The processor contains three external Advanced High-performance Bus (AHB)-Lite bus

interfaces and one Advanced Peripheral Bus (APB) interface:

• ICode memory interface

• DCode memory interface on page 2-5

• System interface on page 2-5

• Private Peripheral Bus (PPB) on page 2-5.

The processor matches the AMBA 3 specification except for maintaining control information

during waited transfers. The AMBA 3 AHB-Lite Protocol states that when the slave is

requesting wait states the master must not change the transfer type, except for the following

cases:

• On an IDLE transfer, the master can change the transfer type from IDLE to NONSEQ.

• On a BUSY transfer with a fixed length burst, the master can change the transfer type

from BUSY to SEQ.

• On a BUSY transfer with an undefined length burst, the master can change the transfer

type from BUSY to any other transfer type.

The processor does not match this definition because it might change the access type from SEQ

or NONSEQ to IDLE during a waited transfer. The processor might also change the address or

other control information and therefore request an access to a new location. The original address

that was retracted might not be requested again. This cancels the outstanding transfer that has

not occurred because the previous access is wait-stated and awaiting completion. This is done

so that the processor can have a lower interrupt latency and higher performance in wait-stated

systems by retracting accesses that are no longer required.

To achieve complete compliance with the AMBA 3 specification you can implement the design

with the AHB_CONST_CTRL parameter set to 1. This ensures that once transfers are issued

during a wait-stated response they are never retracted or modified and the original transfer is

honoured. The consequence of setting this parameter is that the performance of the core might

decrease for wait-stated systems as a result of the interrupt and branch latency increasing.

ICode memory interface

Instruction fetches from Code memory space,

0x00000000

0x1FFFFFFF

, are performed over this

32-bit AHB-Lite bus.

The Debugger cannot access this interface. All fetches are word-wide. The number of

instructions fetched per word depends on the code running and the alignment of the code in

memory.