User guide

Functional Description
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 2-5
ID072410 Non-Confidential
DCode memory interface
Data and debug accesses to Code memory space,
0x00000000 to 0x1FFFFFFF , are performed over
this 32-bit AHB-Lite bus. Core data accesses have a higher priority than debug accesses on this
bus. This means that debug accesses are waited until core accesses have completed when there
are simultaneous core and debug access to this bus.
Control logic in this interface converts unaligned data and debug accesses into two or three
aligned accesses, depending on the size and alignment of the unaligned access. This stalls any
subsequent data or debug access until the unaligned access has completed.
Note
ARM strongly recommends that any external arbitration between the ICode and DCode AHB
bus interfaces ensures that DCode has a higher priority than ICode.
System interface
Instruction fetches, and data and debug accesses, to address ranges
0x20000000 to 0xDFFFFFFF and
0xE0100000 to 0xFFFFFFFF are performed over this 32-bit AHB-Lite bus.
For simultaneous accesses to this bus, the arbitration order in decreasing priority is:
• data accesses
• instruction and vector fetches
• debug.
The system bus interface contains control logic to handle unaligned accesses, FPB remapped
accesses, bit-band accesses, and pipelined instruction fetches.
Private Peripheral Bus (PPB)
Data and debug accesses to external PPB space,
0xE0040000 to 0xE00FFFFF , are performed over
this 32-bit Advanced Peripheral Bus (APB) bus. The Trace Port Interface Unit (TPIU) and
vendor specific peripherals are on this bus.
Core data accesses have higher priority than debug accesses, so debug accesses are waited until
core accesses have completed when there are simultaneous core and debug access to this bus.
Only the address bits necessary to decode the External PPB space are supported on this
interface.
The External PPB (EPPB) space,
0xE0040000 up to 0xE0100000 , is intended for
CoreSight-compatible debug and trace components, and has a number of irregular limitations
which make it less useful for regular system peripherals. ARM recommends that system
peripherals are placed in suitable Device type areas of the System bus address space, with use
of an AHB2APB protocol converter for APB-based devices.
Limitations of the EPPB space are:
• it is accessible in privileged mode only
• it is accessed in little-endian fashion irrespective of the data endianness setting of the
processor
• accesses behave as Strongly Ordered
• no bit-band function is available
• unaligned accesses have Unpredictable results