User guide

Functional Description

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• only 32-bit data accesses are supported

• it is accessible from the Debug Port and the local processor, but not from any other

processor in the system.

2.2.2 ETM interface

The ETM interface enables simple connection of an ETM to the processor. It provides a channel

for instruction trace to the ETM. See the ARM Embedded Trace Macrocell Architecture

Specification.

2.2.3 AHB Trace Macrocell interface

The AHB Trace Macrocell (HTM) interface enables a simple connection of the AHB trace

macrocell to the processor. It provides a channel for the data trace to the HTM.

Your implementation must include this interface to use the HTM interface. You must set

TRCENA to 1 in the Debug Exception and Monitor Control Register (DEMCR) before you

enable the HTM port to supply trace data. See the ARMv7-M Architecture Reference Manual.

2.2.4 Debug Port AHB-AP interface

The processor contains an Advanced High-performance Bus Access Port (AHB-AP) interface

for debug accesses. An external Debug Port (DP) component accesses this interface. The

Cortex-M3 system supports three possible DP implementations:

•The Serial Wire JTAG Debug Port (SWJ-DP). The SWJ-DP is a standard CoreSight debug

port that combines JTAG-DP and Serial Wire Debug Port (SW-DP).

• The SW-DP. This provides a two-pin interface to the AHB-AP port.

• No DP present. If no debug functionality is present within the processor, a DP is not

required.

The two DP implementations provide different mechanisms for debug access to the processor.

Your implementation must contain only one of these components.

Note

Your implementation might contain an alternative implementer-specific DP instead of SW-DP

or SWJ-DP. See your implementer for details.

For more detailed information on the DP components, see the CoreSight Components Technical

Reference manual.

For more information on the AHB-AP, see Chapter 7 Debug.

The DP and AP together are referred to as the Debug Access Port (DAP).

For more detailed information on the debug interface, see the ARM Debug Interface v5

Architecture Specification.