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List of Tables

Cortex-M3 Technical Reference Manual

Change History ............................................................................................................................... ii

Table 1-1 Optional implementation components ......................................................................................... 1-5

Table 3-1 Cortex-M3 instruction set summary ............................................................................................ 3-4

Table 3-2 Memory regions ........................................................................................................................ 3-11

Table 4-1 System control registers ............................................................................................................. 4-3

Table 4-2 ACTLR bit assignments .............................................................................................................. 4-5

Table 4-3 CPUID bit assignments ............................................................................................................... 4-6

Table 4-4 AFSR bit assignments ................................................................................................................ 4-6

Table 5-1 MPU registers ............................................................................................................................. 5-4

Table 6-1 NVIC registers ............................................................................................................................. 6-4

Table 6-2 ICTR bit assignments .................................................................................................................. 6-5

Table 7-1 Cortex-M3 ROM table identification values ................................................................................. 7-3

Table 7-2 Cortex-M3 ROM table components ............................................................................................ 7-4

Table 7-3 SCS identification values ............................................................................................................ 7-5

Table 7-4 Debug registers ........................................................................................................................... 7-5

Table 7-5 AHB-AP register summary .......................................................................................................... 7-6

Table 7-6 CSW bit assignments .................................................................................................................. 7-7

Table 7-7 FPB register summary .............................................................................................................. 7-10

Table 8-1 DWT register summary ............................................................................................................... 8-4

Table 9-1 ITM register summary ................................................................................................................. 9-4

Table 9-2 ITM_TPR bit assignments ........................................................................................................... 9-5

Table 10-1 Cortex-M3 resources ................................................................................................................ 10-4

Table 10-2 Boolean function encoding for events ....................................................................................... 10-5

Table 10-3 Resource identification encoding .............................................................................................. 10-5

Table 10-4 Input connections ...................................................................................................................... 10-7

Table 10-5 Trigger output connections ....................................................................................................... 10-8

Table 10-6 ETM registers ............................................................................................................................ 10-9

Table 10-7 ETMCR bit assignments ......................................................................................................... 10-12

Table 10-8 ETMCCR bit assignments ....................................................................................................... 10-14

Table 10-9 ETMSCR bit assignments ....................................................................................................... 10-15