User guide

Debug
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 7-6
ID072410 Non-Confidential
7.2 About the AHB-AP
The AHB-AP is a Memory Access Port (MEM-AP) as defined in the ARM Debug Interface v5
Architecture Specification. The AHB-AP is an optional debug access port into the Cortex-M3
system, and provides access to all memory and registers in the system, including processor
registers through the SCS. System access is independent of the processor status. Either SW-DP
or SWJ-DP is used to access the AHB-AP.
The AHB-AP is a master into the Bus Matrix. Transactions are made using the AHB-AP
programmers model, which generates AHB-Lite transactions into the Bus Matrix.
7.2.1 AHB-AP transaction types
The AHB-AP does not perform back-to-back transactions on the bus, and so all transactions are
non-sequential. The AHB-AP can perform unaligned and bit-band transactions. The Bus Matrix
handles these. The AHB-AP transactions are not subject to MPU lookups. AHB-AP transactions
bypass the FPB, and so the FPB cannot remap AHB-AP transactions.
AHB-AP transactions are little-endian.
7.2.2 AHB-AP programmers model
Table 7-5 shows the AHB-AP registers. If the AHB-AP is not present, these registers read as
zero. Any register that is not specified in this table reads as zero.
The following sections describe the AHB-AP registers whose implementation is specific to this
processor. Other registers are described in the CoreSight Components Technical Reference
Manual.
AHB-AP Control and Status Word Register, CSW
The CSW characteristics are:
Purpose Configures and controls transfers through the AHB interface.
Usage constraints There are no usage constraints.
Table 7-5 AHB-AP register summary
Offset
a
a. The offset given in this table is relative to the location of the AHB-AP in the DAP memory space. This
space is only visible from the access port. It is not part of the processor memory map.
Name Type Reset
Description
0x00 CSW RW See register AHB-AP Control and Status Word Register, CSW
0x04 TAR RW - AHB-AP Transfer Address Register
0x0C DRW RW - AHB-AP Data Read/Write Register
0x10 BD0 RW - AHB-AP Banked Data Register0
0x14 BD1 RW - AHB-AP Banked Data Register1
0x18 BD2 RW - AHB-AP Banked Data Register2
0x1C BD3 RW - AHB-AP Banked Data Register3
0xF8 DBGDRAR RO 0xE00FF003 AHB-AP ROM Address Register
0xFC IDR RO 0x24770011 AHB-AP Identification Register