User guide

Embedded Trace Macrocell

ID072410 Non-Confidential

10.2.7 Triggering

The ETM provides a trigger resource that can be used to identify a point within a trace run. The

generation of a trigger does not affect the tracing in any way, but the trigger will be output in the

trace stream, and can also be passed to other trace components or used to halt the processor. An

external trace port analyzer can use the trigger to determine when to start and stop capture of

trace.

10.2.8 Interfaces

The ETM-M3 has the following external interfaces:

ATB A 32-bit Advanced Trace Bus provides trace output from the macrocell. See the

AMBA 3 ATB Protocol Specification for more information about this interface.

APB An Advanced Peripheral Bus provides the control interface for the macrocell. See

the AMBA 3 APB Protocol Specification for more information about this

interface.

CTI Your implementation can provide a Cross Trigger Interface to manage the

interconnection of trigger and control signals between the processor core, ETM,

and TPIU. The implementation of your Cortex-M3 processor determines which

ETM functions are visible to the CTI.

Recommended CTI connections

Table 10-4 and Table 10-5 on page 10-8 show the recommended CTI connections for

Cortex-M3 systems.

Note

These tables show the ARM standard connections, but the actual connections are

implementation-defined. Check the documentation from the supplier of your device for any

changes to these connections.

Table 10-4 Input connections

Trigger bit Source signal Source device Comments

[7] ETMTRIGOUT ETM Recommended if ETM is present.

[6] ETMTRIGGER[2] DWT Recommended.

[5] ETMTRIGGER[1] DWT Recommended.

[4] ETMTRIGGER[0] DWT Recommended.

[3] ACQCOMP ETB Recommended if an Embedded Trace Buffer (ETB) is present.

If multiple cores share a single ETB, you must only connect

to the CTI of one of the cores.

[2] FULL ETB

[1] User Defined - -

[0] HALTED Core Compulsory.