Specifications

MDR User Guide 97
FPDP - Digital I/O
An MDR system normally interfaces to its data source with a digital I/O interface based
on the industry standard FPDP (Front Panel Data Port) specification (Proprietary ports
may also be accommodated; please consult factory). The FPDP interface is a 32-bit
synchronous input/output parallel interface which is specified to operate at clock rates
up to 25 MHz (TTL). The FPDP interface is used by a variety of third party vendors with
products such as A/D converters, D/A converters and DSP boards.
DPIO FPDP PMC
The DPIO (Digital Parallel I/O) PMC (PCI Mezzanine Card) module is designed for
high-speed data acquisition and generation. It combines a Digital Parallel Input or
Output on one end, a 32-bit PCI bus master/slave interface with a DMA controller on the
other end, with a large FIFO in between. For more detailed information about the DPIO
PMC module, see the DPIO PMC Module User’s Manual
DPIO Features
• 32-bit input/output FIFOs,
• Synchronous port with FPDP interface,
• Linked-list DMA controller on PCI,
• Personality module for proprietary and user-defined I/O interfaces,
• PLD allows customization, data packing,
• Optional byte swapping,
• 16-bit, 10-bit, 8-bit or 4-bit data packing,
• Up to 108 MiB/sec PCI data rate (sustained).
Current Models
DPIO-FI & DPIO-FO
FPDP Compliant input and output models respectively for TTL level signaling.
• 32-bit parallel I/O TTL up to 25 MHz
• 16-bit parallel I/O TTL up to 40 MHz
DPIO-EI & DPIO-EO
Input and output models for high speed differential signaling using PECL technology.
• 16-bit parallel I/O up to 50 MHz
• 10-bit parallel I/O up to 70 MHz
DPIO-LI & DPIO-LO
Input and output models for differential signaling using LVDS signaling.
• 32-bit parallel I/O LVDS up to 25 MHz
• 16-bit parallel I/O LVDS up to 46.5 MHz
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