Specifications

MDR User Guide 99
DPIO Specifications
Max. input data rate
25 MHz at 32-bits (-FI/FO versions)
40 MHz at 16-bits with 2:1 packing
(-FI/FO versions with PECL strobe)
50 MHz at 16-bits with 2:1 packing
(-EI/EO versions only)
75 MHz at 10-bits with 3:1 packing
(-EI/EO versions only)
75 MHz at 8-bits with 4:1 packing
(-EI/EO versions only)
49 MHz at 32-bits (-LI/LO versions)
Max. PCI transfer
rate
108 MiB/s
FIFO size
8Kx32 or 32Kx32
Cable lengths
1.0m(max), 0.3m, 0.1m (TTL)
10m(max), 5m, 2m (RS422/LVDS)
Operating
Temperature
0 to 70
°C
Greater than 50
°C operation requires
adequate airflow (
≥ LFPM)
Storage Temperature
-40 to +85
°C
Operating Humidity
5% to 95% non-condensing
Storage Humidity
5% to 95% non-condensing
Power consumption
Typical 1.0A / max 1.5A at +5V
Weight
100 grams
DPIO-FI/FO - FPDP
The most common interface for the DPIO is the FPDP (Front Panel Data Port). The
FPDP bus is intended to provide data transfer between two or more VMEbus boards at
up to 160 MiB/s with the lowest possible latency, without compromising existing
VMEbus and other connections on the chassis P1 and P2 connectors. FPDP is connected
by means of an 80-conductor ribbon cable connector at the front panel of the VMEbus
board. The wiring topology is in the form of a bus. Multiple FPDP buses may coexist in
a single VMEbus enclosure.
Details about FPDP can be found in the FPDP Specification at VITA’s web site:
http://www.vita.com.
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