Specifications

102 MDR User Guide
SUSPEND
/SUSPEND is generated by the receiver to inform the data source of a pending FIFO
overflow condition. The data source is allowed as many as 16 cycles before suspending
the transfer. Since /SUSPEND is asynchronous to STROB, the data source should
synchronize it before sampling its state; this avoids stability problems.
This signal is active low :
• Driven to logical “0” to activate SUSPEND,
• Driven to logical “1” to deactivate SUSPEND.
The DPIO of the MDR may activate the Suspend signal to indicate that the DPIO FIFO
is almost full so that the data source should stop sending data until the Suspend signal is
deactivated again. The user may enable or disable the use of the Suspend signal by
setting the
SuspendSignal item in the mdr.ini file.
To disable the Suspend signal, type the following command at the MIDAS Monitor
prompt:
# iset DpioInfo SuspendSignal Disable mdr.ini
To enable the Suspend signal, type the following command at the MIDAS Monitor
prompt:
# iset DpioInfo SuspendSignal Enable mdr.ini
PIO Bits
The DPIO input modules use the PIO signals for synchronization with the data source
when starting/stopping the recording. Generally, either PIO1 or PIO2 signal can be used.
The PIO signal is configured as an output signal from the DPIO input module to signal
the data source that the MDR is ready to start recording/receiving data. The data source
is responsible for not sending data until the PIO signal has been asserted (logical level
“1”). When the recording has finished, the MDR will de-assert PIO (logical level “1” to
“0”) to signal that it is so.
In future versions, the MDR will support functions in the API to allow the user to
control the PIO bits.
NRDY (Not Ready)
The DPIO input module uses NRDY to signal to the data source that a recording has
ended. The NRDY signal works almost the same way as the PIO bits. The difference is
that the NRDY signal is deactivated (DPIO ready to receive) a few micro-seconds
(approximately 3µs) before the PIO signal is activated. The reason for this apparent
redundancy is that the NRDY signal, which is the real data ready signal, is frequently
not available for the user to be used as a system start signal. It is buried at a low
hardware level. However, the PIO, which is a user-controlled signal, is more likely to be
available to the user.
Please note that the DPIO input hardware has no way of activating NRDY right after the
last word of the last recording block has been received. The NRDY bit may only be
controlled by software, and the software has no way of knowing the exact number of
words having been received at any time by the DPIO input module. The DMA controller
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