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CP302 3U CompactPCI Pentium III-based CPU Board Manual ID 21112, Rev. Index 05 Feb 01 The product described in this manual is in compliance with all applied CE standards. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.
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CP302 Preface Table of Contents Preface Manual Table of Contents...................................................................................... 0 - 3 Revision History ................................................................................................... 0 - 14 Trademarks.......................................................................................................... 0 - 14 Explanation of Symbols ..................................................................................
Preface Chapter CP302 2 Functional Description and Configuration 2.1 Functional Block Diagram ............................................................................. 2 - 4 2.2 Front Panels .................................................................................................. 2 - 5 2.3 Board Layouts ............................................................................................... 2 - 6 2.4 Main Features ......................................................................
CP302 Preface 2.6.8 Floppy Drive Interface ...........................................................................2 - 21 2.6.8.1 Floppy Disk Connector CON13 Pinout ..........................................2 - 21 2.6.8.2 PCI Extension Connector CON6 ....................................................2 - 22 2.6.8.3 I/O Interface Connectors CON3 and CON11 .................................2 - 22 2.6.9 CompactPCI Bus Interface(s) ...............................................................2 - 22 2.6.
Preface Chapter CP302 3 Installation 3.1 Board Installation .......................................................................................... 3 - 3 3.1.1 Placement of the CP302 ........................................................................ 3 - 4 3.1.2 EIDE Interfaces. ..................................................................................... 3 - 4 3.1.3 Keyboard/Mouse Connector .................................................................. 3 - 5 3.
CP302 Preface Appendix A I/O Module A.1 Overview ...................................................................................................... A - 3 A.2 Technical Specifications ................................................................................ A - 3 A.3 Module Layouts ............................................................................................. A - 4 A.3.1 Standard I/O Module Layout................................................................... A - 4 A.3.
Preface B.4.3 CP302 CompactPCI Bus Interface.................................................................... B - 9 B.4.3.1 CompactPCI Bus Connectors CON1 and CON2 Pinouts ................ B - 9 B.5 Board Installation ...................................................................................... B - 11 Appendix C IDE2 Module C.1 Overview ........................................................................................................C - 3 C.2 Technical Specifications ..............
CP302 Appendix Preface D CP-RIO3-01 Rear I/O Module D.1 Overview........................................................................................................ D - 3 D.2 Front Panels .................................................................................................. D - 4 D.3 Module Layout: 4HP and 8HP Versions ........................................................ D - 5 D.4 Module Interfaces ......................................................................................
Preface CP302 Figures Figure Number and Title 2-1 CP302 Functional Block Diagram ................................................................. 2 - 4 2-2 CP302 Front Panels ...................................................................................... 2 - 5 2-3 CP302 Board Layout (Front Side) ................................................................. 2 - 6 2-4 CP302 Board Layout (Reverse Side) ............................................................
CP302 Preface C-2 IDE2 Module Layout, Standard Version (Reverse Side) ............................... C - 4 C-3 IDE2 Module Layout, HardDisk Version (Front Side) .................................... C - 5 C-4 IDE2 Module Layout, HardDisk Version (Reverse Side) ............................... C - 5 C-5 PC-Compatible D-sub Serial Interface .......................................................... C - 6 C-6 PC-Compatible Parallel Interface ..................................................................
Preface 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 2-32 2-33 2-34 2-35 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 A-1 CP302 CompactPCI Bus Connector J1 (CON1) Pinout ........................................ 2 - 23 64-bit CompactPCI Bus Connector J2 (CON2) Pinout .............................. 2 - 24 Rear I/O CompactPCI Bus Connector J2 (CON2) Pinout ......................... 2 - 27 External BIOS Setting .....................................
CP302 Preface A-2 Serial Port Connectors CON2 and CON6 Pinouts (RS232 Mode) ................ A - 6 A-3 Serial Port Connectors CON2 and CON6 Pinouts (RS422 Mode) ................ A - 7 A-4 26-Pin MDR Connector CON4 Pinout ........................................................... A - 8 A-5 Pinout of the AT 44-pin EIDE Connector CON5............................................ A - 9 A-6 Pinout of the AT Standard EIDE Connector CON9 .....................................
Preface CP302 Revision History Revision History Manual/Product Title: CP302 Manual ID Number: 21112 Rev. Index Brief Description of Changes Board Index Date of Issue 0100 Initial Issue 00 Apr. 00 0200 Inclusion of Minor Improvements 00 Jul. 00 03 General manual revision and update including addition of chapters for IDE2 module and Rear I/O modules 00 Nov. 00 04 Restructuring of Table of Contents 00 Nov. 00 05 Correction of technical problem in IDE2 chapter 00 Feb.
CP302 Preface Explanation of Symbols CE Conformity This symbol indicates that the product described in this manual is in compliance with all applied CE standards. Please see also the section “Applied Standards” in this manual. Caution! This symbol and title warn you of hazards due to electrical shocks (> 60 V) when touching products or parts of them. Failure to observe the necessary precautions as described and/or prescribed by the law may result in damage to your product and/or endanger your life/health.
Preface CP302 For your safety Your new PEP product has been developed and carefully tested in order to provide all the features necessary to ensure full compliance with all electrical safety requirements. It has also been designed for a long fault-free life. However, the life expectancy of your product will be drastically reduced by improper treatment during unpacking and installation.
CP302 Preface General Instructions on Usage $ In order to maintain PEP’s product warranty, this product must not be altered or modified in any way. Changes or modifications to the device, which are not explicitly approved by PEP Modular Computers and described in this manual or received from PEP Technical Support as a special handling instruction, will void your warranty.
Preface CP302 Two Year Warranty PEP Modular Computers grants the original purchaser of a PEP product a TWO YEAR LIMITED as described in the following. However, no other warranties that may be granted or implied by anyone on behalf of PEP are valid unless the customer has the express written consent of PEP Modular Computers.
CP302 Introduction Chapter 1 Introduction 1.1 Introduction to CompactPCI ..........................................................................1 - 3 1.2 PEP Single-height CPU Boards ....................................................................1 - 4 1.3 CP302 Product Overview ..............................................................................1 - 4 1.4 CP302 Board Introduction .............................................................................1 - 5 1.
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CP302 Introduction 1. Introduction 1.1 Introduction to CompactPCI The PEP Modular Computers CompactPCI product described in this chapter operates with the PCI bus architecture to support additional I/O and memory-mapped devices as required by various industrial applications. For detailed information concerning the CompactPCI standard, please consult the complete Peripheral Component Interconnect (PCI) and CompactPCI Specifications.
CP302 Introduction 1.2 PEP Single-height CPU Boards Socket 7 Family The CP312 is a highly integrated 32bit/33 MHz CompactPCI single-board computer that is designed around the Pentium family from Intel and AMD’s K6™ microprocessors. The VGA interface is integrated within the Chipset. To achieve high CPU and memory performance the board includes 512 kB L2 Cache. DRAM is 32 MB or 64 MB (soldered) which together with the SODIMM provides up to 128 MB main memory.
CP302 Introduction 1.4 CP302 Board Introduction The CP302 is a CompactPCI Mobile PentiumIIl Coppermine™ based single-board computer specifically designed for use in highly integrated platforms with solid mechanical interfacing for a wide range of industrial environment applications. Some of the CP302’s outstanding features are: • • • • • • • • • • • • compliance with CompactPCI Interface 2.0 R3.
CP302 Introduction 1.
CP302 Introduction Table 1-1: CP302 Main Specifications CP302 Specifications Rear I/O When the Rear I/O is enabled the CompactPCI interface is configured for 32-bit/33 MHz The 32-bit CompactPCI bus has Rear I/O capability. The following interfaces are routed to the Rear I/O connector J2: COM1 and COM2, PS/2 mouse and keyboard, 2xUSB’s, CRT VGA, Ethernet and secondary EIDE port. PMC Interface PCI mezzanine connector for standard PMC module. 32-bit/33 MHz master interface 3.3V/5.
CP302 Introduction 1.6 Power Consumption and Temperature Range The CP302 board is based on the Intel Mobile PentiumIIl processor. Intel has developed mobile processors to meet the specific needs of mobile PC's. As such, they operate at lower voltages than their desktop counterparts, are significantly smaller in size, consume less power and dissipate less heat. The design is optimized for low power consumption applications.
CP302 Introduction Table 1-3: Power Consumption Table with Windows NT 4.0 Running (no application started and without keyboard) Power 5V 3.3V Total 400 MHz 32 or 64 MB Memory (128 Mbit chips) without VGA 1.2W 4.7W 5.9W 400 MHz 64 or 128 MB Memory with VGA 1.2W 5.9W 7.1W 500 MHz 64 or 128 MB Memory without VGA 1.4W 5.9W 7.3W 700 MHz 64 or 128 MB Memory without VGA 2.0 W 5.8 W 7.8 W The 400 MHz version without VGA is not a standard version. For more information please contact PEP.
CP302 1.6.1 Introduction Temperature Range The CP302 family are the first CompactPCI boards capable of operating over the extended temperature range from -40°C up to + 85°C. All onboard components are specially selected for the higher temperature range. For the higher temperatures the desktop processors are not suitable, because the power consumption is higher and the allowable case temperature is lower. The only suitable processor is the Intel Mobile PentiumIIl processor family.
CP302 Introduction ! Important: It is the responsibility of the end user to ensure that the processor case temperate never exceeds 100° Celsius in order to protect the board against overheating. Permanent overheating can damage the board. If the temperature on the processor die is greater than 100°C the maximum ambient temperature must be reduced or an external airflow must be provided by means of an additional fan. 1.
CP302 Introduction 1.8 Applied Standards 1.8.1 CE Compliance The PEP Modular Computers’ CompactPCI systems comply with the requirements of the following CE-relevant standards: • • • Emission Immission Electrical Safety 1.8.2 • EN50081-1 EN50082-2 EN60950 Mechanical Compliance Mechanical Dimensions 1.8.3 IEEE 1101.10 Environmental Tests • Vibration/Broad-Band Random Vibration IEC68-2-6 IEC68-2-64 (3U boards) • • Permanent Shock Single Shock IEC68-2-29 IEC68-2-27 1.9 Related Publications 1.
CP302 Functional Description and Configuration Chapter 2 Functional Description and Configuration 2.1 Functional Block Diagram ..............................................................................2 - 4 2.2 Front Panels ..................................................................................................2 - 5 2.3 Board Layouts ...............................................................................................2 - 6 2.4 Main Features .......................................
CP302 Functional Description and Configuration Functional Description and Configuration 2.6.4 Fast Ethernet Interface ......................................................................... 2 - 17 2.6.4.1 RJ45 Connector CON10 Pinout .................................................... 2 - 17 2.6.5 Ethernet LED Status ............................................................................ 2 - 17 2.6.6 Fan Power Supply ................................................................................
CP302 Functional Description and Configuration Functional Description and Configuration 2.7.7 Jumper Setting for Rear I/O...................................................................2 - 32 2.7.8 Reserved Jumpers ................................................................................2 - 33 2.8 Memory Map ................................................................................................2 - 33 2.9 Special Registers Description .....................................................
CP302 Functional Description and Configuration 2. Functional Description and Configuration 2.
CP302 Functional Description and Configuration 2.2 Front Panels The front panel includes one LED placed under the keyboard/mouse interface connector (“Board LED’s”) and two LED’s placed over the Ethernet connector (“Ethernet LED”). The functions of the LED’s are as follows: Board LED: • TH (red) = Temperature alarm; if ON, an overtemperature has occurred. The CPU clock speed is reduced automatically.
CP302 Functional Description and Configuration 2.
CP302 Functional Description and Configuration Figure 2-4: CP302 Board Layout (Reverse Side) Note that this diagram is not to scale with the Front Side Board Diagram R314 J6 J7 J3 LOGIC 3 1 2 2 1 3 J5 R291 R298 R286 R302 NW15 NW20 R285 R293 R296 R303 MAGNIFIED SECTION MAGNIFIED SDRAM J8 J9 NW15 NW20 CON2 ID 21112, Rev. 05 CON1 ® PEP Modular Computers GmbH Page 2 - 7 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.
CP302 Functional Description and Configuration 2.4 Main Features The following descriptions highlight the main features of the principal functional blocks of the CP302. 2.4.1 CPU The CP302 supports the Intel Mobile PentiumIIl Coppermine™ processor family up to 700MHz with 256 kB L2 on-die cache in a 495-pin BGA2 package. The processor speed is automatically selected. The onboard voltage regulator is automatically programmed by the processor's VID pins to provide the required voltage.
CP302 Functional Description and Configuration 2.5 Peripherals The following standard peripherals are available on the CP302 board: • Real-Time Clock The real-time clock performs time-keeping functions and includes 256 bytes of general purpose battery-backed CMOS RAM. Features include an alarm function, programmable periodic interrupt and a 100-year calendar. All battery-backed CMOS RAM data remains stored in an additional EEPROM. This prevents data loss.
CP302 Functional Description and Configuration ! Important • Care must be taken to ensure that the battery is correctly replaced. • The battery should be replaced only with an identical or equivalent type recommended by the manufacturer. • Dispose of used batteries according to the manufacturer’s instructions. • The typical life expectancy of a 170 mAh battery (VARTA CR2025) is 4 - 5 years with an average on-time of 8 hours per working day at an operating temperature of 30°C.
CP302 2.5.4 Functional Description and Configuration SMBus Devices The CP302 provides a System Management Bus (SMBus) for access to several system monitoring and configuration functions. The SMBus consists of a two-wire I2C bus interface. The following table describes the function and address of every onboard SMBus device. Table 2-2: SMBus Device Addresses Device SMB Address PIIX4 slave port 0001000Xb Temperature sensor MAX1617 0011000Xb Hardware Monitor LM81 0101100Xb EEPROM 1010XXXXb 2.5.
CP302 Functional Description and Configuration 2.5.6 Serial EEPROM A serial EEPROM is provided, organised into 4 blocks with 256 bytes per block (24LC08). This EEPROM is connected to the I2C™ bus provided by the PIIX4E.
CP302 Functional Description and Configuration 2.5.7 Flash Memory There are two Flash devices available as described below, one for the BIOS and one 32-pin socket for a flexible Flash configuration. 1. BIOS Flash The CP302 uses a 256 kB flash memory to store BIOS firmware. It can be updated as new versions of the BIOS become available. You may easily upgrade your BIOS using the AWARD awdflash utility . 2. Socket Memory Different flash module versions are available.
CP302 Functional Description and Configuration 2.6 Board Interfaces 2.6.1 Keyboard/Mouse Interface The onboard keyboard controller is 8042 software compatible. 4 6 Figure 2-5: Keyboard/Mouse Connector The PC/AT standard keyboard/mouse connector is a PS/2-type 6-pin shielded mini-DIN connector. The keyboard power supply unit is protected by a 500 mA fuse. All signal lines are EMI-filtered. 2 1 5 3 2.6.1.
CP302 2.6.2 Functional Description and Configuration USB Interface The Universal Serial Bus, or USB, is a versatile port. This one port type can function as a serial, parallel, mouse, keyboard, or joystick port and is capable of supporting up to 127 daisy-chained peripheral devices. Figure 2-6: USB Connector One USB interface with a maximum transfer rate of 12 Mbit is provided. One USB peripheral may be connected to this port. To connect one or more USB devices an external hub is required.
CP302 Functional Description and Configuration 2.6.3 VGA Interface Figure 2-7: D-sub VGA Connector 10 15 5 11 1 The CP302 is equipped with the 69030 VGA chip with 4 MB memory. This contains an SVGA controller that is fully compatible with the CGA, EGA, Hercules Graphics, MDA, and VGA video standards. The controller connects directly to the onboard 66 MHz AGP Interface with a maximum data transfer rate of 266 MB/sec. The video controller supports pixel resolutions of up to 1600 x 1200 or up to 16.
CP302 2.6.4 Functional Description and Configuration Fast Ethernet The CP302 board includes a 10BASE-T/100BASE-TX network solution based on the Intel 82559 Fast Ethernet PCI Bus Controller. The controller contains two receive and transmit FIFO buffers that prevent data overruns or underruns while waiting for access to the PCI bus. Two LED’s monitor network conditions. The Boot from LAN feature is supported, for details please refer to section 4.5, BIOS Features Setup, in chapter 4.
CP302 2.6.6 Functional Description and Configuration Fan Power Supply A fan for CPU cooling may be connected through the power connector J2. Table 2-8: Fan Power Supply J2 Function 1 GND 2 +5V or +12V Please see table 2-17 on page 2-31 for necessary jumper setting 3 Sense input 2.6.7 EIDE Interfaces The two EIDE interfaces support PIO mode 4 with transfers up to 14 MB per second and Bus Master Ultra-DMA 33 transfer up to 33 MB per second.
CP302 Functional Description and Configuration 2.6.7.1 EIDE Connector CON7 Pinout The following table sets out the pinout of the CON7 connector, giving the corresponding signal names. The maximum length of cable that may be used is 35 cm. The colored stripe on a ribbon cable (pin 1) from the EIDE1 port should face towards the SODIMM socket.
CP302 Functional Description and Configuration Table 2-9: AT Standard Connector CON7 Pinout Pin Signal Function In/Out 26 GND Ground signal -- 27 IOCHRDY I/O channel ready In 28 GND Ground signal -- 29 IDEDACKA DMA Ack Out 30 GND Ground signal -- 31 IDEIRQ Interrupt request In 32 N/C -- -- 33 A1 Address 1 Out 34 N/C -- -- 35 A0 Address 0 Out 36 A2 Address 2 Out 37 HCS0 HD select 0 Out 38 HCS1 HD select 1 Out 39 LED LED driving In 40 GND Ground
CP302 Functional Description and Configuration 2.6.8 Floppy Drive Interface The onboard floppy disk controller supports either 5.25 inch or 3.5 inch (1.44 or 2.88 MB) floppy disks. A 20-pin male connector provides the signals for an optional floppy-drive that can be installed by means of a special adapter. 2.6.8.
CP302 Functional Description and Configuration 2.6.8.2 PCI Extension Connector CON6 The PCI extension connector (CON6) provides all the necessary PCI signals for the CP302 PMC module. 2.6.8.3 I/O Interface Connectors CON3 and CON11 The I/O interface connectors (CON3 and CON11) provide all necessary signals for the CP302 I/O module. 2.6.
CP302 2.6.9.1 Functional Description and Configuration CompactPCI Connectors CON1 and CON2 Pinouts The CP302 is provided with two 2 mm x 2 mm pitch female CompactPCI bus connectors, J1 and J2. Table 2-11: CompactPCI Bus Connector J1 (CON1) Pinout Pin Row A Row B Row C Row D Row E Row F 25 5V REQ64* ENUM* 3.3V 5V GND 24 AD[1] 5V V(I/O) AD[0] ACK64* GND 23 3.3V AD[4] AD[3] 5V AD[2] GND 22 AD[7] GND 3.3V AD[6] AD[5] GND 21 3.
CP302 Functional Description and Configuration Table 2-12: 64-bit CompactPCI Bus Connector J2 (CON2) Pinout Pin Row Z Row A Row B Row C Row D Row E Row F 22 GND GA4 GA3 GA2 GA1 GA0 GND 21 GND CLK6 GND RSV RSV RSV GND 20 GND CLK5 GND RSV GND RSV GND 19 GND GND GND RSV RSV RSV GND 18 GND RSV RSV RSV GND RSV GND 17 GND RSV GND PRST# REQ6# GNT6# GND 16 GND RSV RSV DEG# GND RSV GND 15 GND RSV GND FAL# REQ5# GNT5# GND 14 GND AD[35] AD[34
CP302 Functional Description and Configuration 2.6.10 Rear I/O Interface The CP302 board provides optional Rear I/O connectivity for peripherals for special compact systems. Some standard PC interfaces are implemented and assigned to the front panel and to the rear connector J2. When the Rear I/O module is used, the signals of some of the main board/front panel connectors are routed to the module interface.
CP302 Functional Description and Configuration 2.6.10.1 Rear I/O Configuration Illustration Figure 2-9: CP302 Rear I/O Configuration Page 2 - 26 ® PEP Modular Computers GmbH ID 21112, Rev. 05 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.
CP302 Functional Description and Configuration 2.6.10.2 Optional Rear I/O interface on Compact PCI Connector CON2 The CP302 conducts a wide range of I/O signals through the Rear I/O connector J2. $ Note: If the Rear I/O feature is selected the PCI interface is only 32-bit. For the 3U Rear I/O a special backplane is necessary.
CP302 Functional Description and Configuration Legend for table on preceding page: 1) Ethernet, SMBUS, Keyboard, Mouse, USB and Power (64-bit and Rear I/O possible) 2) COM1, COM2 (only 32-bit and Rear I/O) 3) VGA Signals (only 32-bit and Rear I/O) 4) EIDE Port (only 32-bit and Rear I/O) 5) Reserved The greyed table cells indicate the power grouping 2.6.10.3 Rear I/O Jumper Setting Rear I/O interfaces are only available on Rear I/O versions of the board.
CP302 Functional Description and Configuration VGA Interface The VGA signals are available on J2 when the board is ordered for Rear I/O configuration. In this configuration both interfaces are active. The 75 ohm termination resistor for the red, green and blue video signals are equipped on the CP302. $ Note: Both VGA ports are electrically identical and not separated. Do not connect devices at both connectors (front I/O and Rear I/O) at the same time.
CP302 Functional Description and Configuration 2.7 Jumper Description 2.7.1 External BIOS It is possible to redirect the first CPU fetch from the onboard flash to the Flash socket. If jumper J1 is open, the board boots from the BIOS in the onboard flash memory. When J1 is closed, the board boots from the socket flash. Table 2-14: External BIOS Setting J1 Function Comment Closed External Bios Use this setting only if the onboard flash does not work.
CP302 Functional Description and Configuration 2.7.4 Fan Power Supply Selection The voltage for the CPU cooling fan can be configured using jumpers J8 and J9 Table 2-17: Fan Power Supply Selection J9 J8 Function Closed Open +5V Open Closed +12V The default setting is indicated by italics 2.7.5 PCI VI/O setting The CP302 provides for either a 5V or 3.3V PCI signaling environment. The BVI/O power jumpers on the board are used to power the buffers on the peripheral boards and the PMC interface.
CP302 Functional Description and Configuration 2.7.7 Jumper Setting for Rear I/O Rear I/O interfaces are only available on Rear I/O versions of the board. In order to implement the system Rear I/O feature, a system slot Rear I/O backplane is necessary. This backplane must comply with the CompactPCI Specification PICMG 2.0 R3.0, October 1999. Warning: ! If the board is ordered for 64-bit CompactPCI the Rear I/O feature is not supported.
CP302 Functional Description and Configuration VGA Interface The VGA signals are available on J2 when the board is ordered for Rear I/O configuration. In this configuration both interfaces are active. The 75 ohm termination resistor for the red, green and blue video signals are equipped on the CP302. Table 2-21: VGA Interface Configuration Configuration $ 2.7.8 Location 75 Ohm for red R51 75 Ohm for green R40 75 Ohm for blue R32 Note: Both VGA ports are electrically identical and not separated.
CP302 Functional Description and Configuration Table 2-23: I/O Address Map Address Range (Hex.
CP302 Functional Description and Configuration 2.9 Special Registers Description The following registers are special registers for the CP302 to watch the onboard hardware special features and the CompactPCI control signals. Normally, only the system BIOS uses these registers, but they are documented here for application use as required. Take care when modifying the contents of these registers as the system BIOS may be relying on the state of the bits under its control. 2.9.
CP302 Functional Description and Configuration 2.9.1.2 Watchdog Timer The CP302 has one watchdog timer with a programmable timeout ranging from 125 msec. to 256 sec. The I/O location for the watchdog configuration is 0x282. Table 2-24: Watchdog Configuration Bits Type Default Function 7-5 R 0 Reserved 4 RW 0 1 = enable watchdog (write) 0 = disable watchdog (read only) 0 The nominal timeout period is 20% longer than the minimum.
CP302 Functional Description and Configuration 2.9.3 Interrupt Configuration Register The interrupt configuration register holds a series of bits defining the interrupt routing for the watchdog, the power control derate signal and the CompactPCI enumeration signal. If the watchdog timer timesout, it can generate three independent hardware events: reset, SMI and IRQ5 interrupt. The enumeration signal is generated by a hotswap compatible board after insertion and prior to removal.
CP302 Functional Description and Configuration 2.9.4 I/O Status This register describes the local and CompactPCI control signals. The watchdog status bit indicates the status of the watchdog timer. If the timer is not re-triggered within the previously set time period, the bit is set to “0”. The fail signal is an output of the power supply indicating a power supply failure. For the description of the derate and enumeration signals please see the interrupt routing register.
CP302 Functional Description and Configuration 2.9.6 Hardware Index The hardware index will signal to the software when differences in the hardware require different handling by the software. It starts with the value 0 and will be incremented with each change in hardware as development continues. I/O location 0x289 Table 2-29: Hardware Index Bits 7-0 Type Default R 2.9.7 Function Revision ID 0 = Index 0000 -- Jumper Status This register can be used to read the onboard jumper configuration.
CP302 Functional Description and Configuration 2.9.8 Logic Version The logic version register may be used to identify the logic status of the board by software. It starts with the value 0 and will be incremented with each logic update. I/O location 0x28B Table 2-31: Logic Version Bits 7-0 Type R 2.9.9 Default Function Logic version 0 = Index 0000 -- PCI Interrupt Routing This register is used by the CPU to control the PCI interrupt routing.
CP302 Functional Description and Configuration 2.9.10 Memory Management of Flash Socket Flash devices which may be mounted in socket IC6 are accessed in paged mode, up to 512 kB are addressable in total. The page size depends on the setting of the Flash Socket Page Register; the Flash access is 8 pages with 64 kB, 16 pages with 32 kB or 64 pages with 8 kB. The Memory Management Register should be used to select the individual pages. The I/O location is 0x28E.
CP302 Functional Description and Configuration 2.10 Video Resolutions The CP302 supports different video resolutions to produce different display parameters. A complete list of possible video resolutions and the relating display parameters is shown in the following table: Table 2-35: Video Resolutions and Display Parameters Resolution Color Depth Bits per Pixel Colors Total Refresh Rate Comments 640 x 480 24 16.7 M 60, 75, 85 True color 800 x 600 24 16.
CP302 Installation Chapter 3 Installation 3.1 Board Installation ...........................................................................................3 - 3 3.1.1 Placement of the CP302 .......................................................................3 - 4 3.1.2 EIDE Interfaces. ....................................................................................3 - 4 3.1.3 Keyboard/Mouse Connector .................................................................3 - 5 3.
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CP302 Installation 3. Installation 3.1 Board Installation Caution! If your board type is not specifically qualified as hotswap capable, please switch off the CompactPCI system before installing the board in a free CompactPCI slot. Failure to do so could endanger your life/health and may damage your board or system. $ Note: Certain CompactPCI boards require bus master and/or Rear I/O capability.
CP302 Installation 3.1.1 Placement of the CP302 The PEP CompactPCI system configuration is characterized by the fact that its system slot (slot “1”) is on the right end of the backplane, thus allowing for physical CPU growth (heat-sink, cooling fan etc.) associated with higher-performance processors. $ 3.1.2 Important! After having inserted your controller board, please make sure it has been fitted into the system slot. EIDE Interfaces.
CP302 Installation 3.1.3 Keyboard/Mouse Connector The CP302 uses a PC/AT standard keyboard/mouse connection realized as a 6-pin shielded mini-DIN connector. To connect both a mouse and keyboard to your mini-DIN connector, a suitable keyboard/mouse Y-adapter may be used ! Attention When plugging in your keyboard and mouse, or when plugging anything into a Serial or Com port, make sure that the power is off.
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CP302 CMOS Setup Chapter 4 CMOS Setup 4.1 Proprietary Notice ..........................................................................................4 - 3 4.2 Introduction to Setup .....................................................................................4 - 3 4.3 Main Setup Menu ...........................................................................................4 - 7 4.4 Standard CMOS Setup ..................................................................................4 - 9 4.
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CP302 CMOS Setup 4. CMOS Setup This chapter describes the Award BIOS Setup program, EliteBIOS, version 4.51PG. The Setup program lets you modify basic system configuration settings. 4.1 Proprietary Notice Unless otherwise noted, chapter 4 of this manual, which concerns the EliteBIOS setup program, as well as the information herein disclosed are proprietary to AWARD Software International, Inc.
CP302 CMOS Setup Starting Setup The Award BIOS is immediately activated when you first turn on the computer. The BIOS reads system configuration information in CMOS RAM and begins the process of checking out the system and configuring it through the Power-on Self Test (POST). When these preliminaries are finished, the BIOS seeks an operating system on one of the data storage devices (hard drive, floppy drive, etc.). The BIOS launches the operating system and hands control of system operations to it.
CP302 CMOS Setup Setup Keys The following table describes how to navigate in Setup using the keyboard. Table 4-1: Keyboard Commands Up Arrow Down Arrow Move to previous item Move to next item Left Arrow Move to the item to the left Right Arrow Move to the item to the right Esc Key Main Menu: Quit without saving changes into CMOS RAM.
CP302 CMOS Setup Getting Help Press F1 and a small help window pops up that describes the appropriate keys to use and the possible selections for the highlighted item. To exit the Help Window press or the F1 key again. In Case of Problems If, after making and saving system changes with Setup, you discover that your computer is no longer able to boot, the Award BIOS supports an override to the CMOS settings that resets your system to its default configuration.
CP302 CMOS Setup 4.3 Main Setup Menu When you enter the Award BIOS CMOS Setup Utility, a Main Menu, similar to the one shown below, appears on the screen. The Main Menu allows you to select from several Setup functions and two exit choices. Use the arrow keys to select items and press ↵ to accept and enter the sub-menu. Figure 4-1: CMOS Setup Utility Main Menu — Screen Display A brief description of each highlighted selection appears at the bottom of the screen.
CP302 CMOS Setup Integrated Peripherals I/O subsystems, that depend on the integrated peripherals controller in your system. Special Features Setup Items related to features of this board, which are not common to standard motherboard designs. Supervisor/User Password Change, set, or disable a password. In BIOS versions that allow separate user and supervisor passwords, only the supervisor password permits access to Setup. The user password generally allows only power-on access.
CP302 CMOS Setup 4.4 Standard CMOS Setup In the Standard CMOS menu you can set the system clock and calendar, record disk drive parameters and the video subsystem type, and select the type of errors that stop the BIOS POST. Date The BIOS determines the day of the week from the other date information. This field is for information only. Press the → or ← key to move to the desired field (date, month, year). Press the “PgUp” or “PgDn” key to increment the setting, or type the desired value into the field.
CP302 CMOS Setup The BIOS has the capability to automatically detect the specifications and optimal operating mode of almost all EIDE hard drives. When you select type AUTO for a hard drive, the BIOS detects its specifications during POST, every time the system boots. If you do not want to select drive type AUTO, other methods of selecting the drive type are available as follows: 1. Match the specifications of your installed EIDE hard drive(s) with the preprogrammed values for drive types 1 through 45.
CP302 CMOS Setup Drive A / Drive B Selects the correct specifications for the diskette drive(s) installed in the computer. Table 4-3: Diskette Drives No diskette drive installed None 360K, 5.25 in 5-1/4 inch PC-type standard drive; 360 kilobyte capacity 1.2M, 5.25 in 5-1/4 inch AT-type high-density drive; 1.2 megabyte capacity 720K, 3.5 in 3-1/2 inch double-sided drive; 720 kilobyte capacity 1.44M, 3.5 in 3-1/2 inch double-sided drive; 1.44 megabyte capacity 2.88M, 3.
CP302 CMOS Setup Halt On During the power-on self-test (POST), the computer stops if the BIOS detects a hardware error. You can program the BIOS to ignore certain errors during POST and continue the boot-up process. The possible selections are listed in the following table. Table 4-5: POST Specific Commands Command POST Action No errors POST does not stop for any errors. All errors If the BIOS detects any non-fatal error, POST stops and prompts you to take corrective action.
CP302 CMOS Setup 4.5 BIOS Features Setup This screen contains industry-standard options additional to the core PC AT BIOS. This section describes all fields presented by Award Software in this screen.
CP302 CMOS Setup Boot from LAN first If Your BIOS if capable of Booting from LAN via DHCP/BOOTP – protocol (option), you can switch this option on/off here. Boot Sequence The original IBM PC’s loaded the operating system from drive A (floppy disk), so IBM PC-compatible systems are designed to search for an operating system first on drive A, and then on drive C (HardDisk). However, modern computers usually load the operating system from the hard drive, and may even load it from a CD-ROM drive.
CP302 CMOS Setup Typematic Rate (Chars/Sec) When the typematic rate setting is enabled, you can select a typematic rate (the rate at which a character repeats when you hold down a key) of 6, 8, 10, 12, 15, 20, 24 or 30 characters per second. Typematic Delay (ms) When the typematic rate setting is enabled, you can select a typematic delay (the delay before key strokes begin to repeat) of 250, 500, 750 or 1000 milliseconds.
CP302 CMOS Setup Socket Window Page The CP302 is equipped with a 32-pin socket to take additional Flash-ROM. This FlashROM may be addressed by a paging mechanism. The size of one Flash page can be set at this point as follows: Table 4-6: Setting Flash Page Size Page Size Address Space used by Socket Flash EPROM 8 KB 0xDE000 - 0xDFFFF 32 KB 0xD8000 - 0xDFFFF 64 KB 0xD0000 - 0xDFFFF Award Preboot Agent Agent software may be enabled and disabled. The default is Disabled.
CP302 CMOS Setup Agent Host Drive A When the administrative host is using the Preboot Manager application, the Agent can boot and run applications from host floppy drive A. INT13 calls intended for the Agent floppy drive A are redirected by the Agent extension to the host floppy drive A. All other INT13 calls are passed along to the original interrupt handler. The Manager application can receive the Agent drive A interrupt and interpret the commands.
CP302 CMOS Setup 4.6 Chipset Features Setup This section describes features of the PIIX4 PCIset. If your system contains a different chipset, this section will bear little resemblance to what you see on your screen.. PEP Advantage This section describes all the fields presented on this screen display. Please note that your system board designer may omit or modify some of the fields described in the following.
CP302 CMOS Setup SDRAM RAS Precharge Time The precharge time is the number of cycles it takes for the RAS to accumulate its charge before DRAM refresh. If insufficient time is allowed, refresh may be incomplete and the DRAM may fail to retain data. SDRAM CAS Latency Time When synchronous DRAM is installed, you can control the number of CLK’s between the SDRAM’s sample of a read command and the time when the controller samples read data from the SDRAM’s.
CP302 CMOS Setup Passive Release When Enabled, CPU to PCI bus accesses are allowed during passive release. Otherwise, the arbiter only accepts another PCI master access to local DRAM. Delayed Transaction The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification version 2.1. AGP Aperture Size (MB) Select the size of the Accelerated Graphics Port (AGP) aperture.
CP302 CMOS Setup 4.7 Power Management PEP Advantage This section describes all fields presented on this screen display. Please note that your system board designer may omit or modify some of the fields described in the following. Figure 4-6: Power Management Setup — Screen Display. ACPI Function Select Enabled only if your computer’s operating system supports the Advanced Configuration and Power Interface (ACPI) specification. Currently, Windows 98, Windows 2000 and Windows NT support ACPI.
CP302 CMOS Setup Power Management This option allows you to select the type (or degree) of power saving for Doze, Standby, and Suspend modes. See the section PM Timers for a brief description of each mode. The following table describes each power management mode: Table 4-7: Power Management Modes Mode Description Max. Saving Maximum power savings. Only Available for SL CPU’s. Inactivity period is 1 minute in each mode. User Defined Sets each mode individually.
CP302 CMOS Setup 4.8 PM Timers The following modes are Green PC power saving functions. They are user-configurable only during User Defined Power Management mode. Doze Mode After the selected period of system inactivity (1 minute to 1 hour), the CPU clock runs at a slower speed while all other devices still operate at full speed.
CP302 CMOS Setup IRQ8 Break (Event From) Suspend You can select Enabled or Disabled for monitoring of IRQ8 (the Real Time Clock) so that it does not awaken the system from Suspend mode. Reload Global Timer Events When Enabled, an event occurring on each of the devices listed below restarts the global timer for Standby mode: • • • • • • • • • 4.9 IRQ§-7, 9-15, NM1, Primary EIDE 0, Primary EIDE 1, Secondary EIDE 0, Secondary EIDE 1, Floppy Disk, Serial Port, Parallel Port, and IRQ9 (IRQ2 Redir).
CP302 CMOS Setup PNP OS Installed Select “Yes” if the system operating environment is PlugandPlay aware (e.g. Win 95). Resources Controlled by The Award PlugandPlay BIOS can automatically configure all the boot and PlugandPlay-compatible devices. If you select Auto, all the interrupt request (IRQ) and DMA assignment fields disappear, as the BIOS automatically assigns them. Reset Configuration Data Normally this field is left Disabled.
CP302 CMOS Setup Reset PCI-to-PCI Bridges The BIOS may reset the PCI-to-PCI Bridges in the system using a software reset mechanism. Especially in conjunction with Hotswap compatible boards, it should be disabled. Default is disabled. PCI Class Code FFh: Some PCI boards generate a class code 0FFh. Although this code does not conform with the PCI standard, boards of this kind are distributed by some vendors.
CP302 CMOS Setup EIDE 32-bit Transfer Mode Enables or disables 32-bit Data transfers. On-Chip PCI EIDE (Primary/Secondary) The Intel 82C440BX chipset contains a PCI EIDE interface with support for two EIDE channels. Select Enabled to activate the primary and/or secondary EIDE interface. Select Disabled to deactivate this interface if you instal a primary and/or secondary addin EIDE interface.
CP302 CMOS Setup ECP Mode Use DMA Select a DMA channel for the parallel port for use during ECP mode. Watchdog Timer Select the watchdog routing. WDT Active for Booting Select Enable if the watchdog timer requires to be started before the operating system is booted from the BIOS. WDT Active Time Select the time after which the action selected occurs, if the watchdog timer is not retriggered. Page 4 - 28 ® PEP Modular Computers GmbH ID 21112, Rev. 05 Artisan Technology Group - Quality Instrumentation .
CP302 CMOS Setup 4.11 Special Setup Features $ Important! This section describes all the fields presented by Award Software in this screen display. Your system board designer may omit or modify some fields. Figure 4-9: Special Features Setup — Screen Display System Slot This is a display only field. Yes indicates that this CPU is the system controller configuring the backplane and handling all interrupts relating to the backplane. No indicates that this CPU is a slave CPU.
CP302 CMOS Setup 4.12 Password Setting When you select this function, the following message appears at the center of the screen: Enter password: Type the password, up to eight characters in length, and press “↵”. Typing a password clears any previously entered password from the CMOS memory. After having pressed “↵” the message changes to: Confirm password: Type the password again and press “↵”. To abort the process at any time, press “Esc”.
CP302 CMOS Setup 4.13 POST Messages During the Power-on Self Test (POST), the BIOS displays a message whenever it detects a correctable error. Any error message is followed by this prompt: Press “F1” to continue, “Ctrl-Alt-Esc” or “Del” to enter setup. Following is a list of POST error messages for both the ISA and the EISA BIOS. CMOS Battery Has Failed The CMOS battery is no longer functional. It should be replaced. CMOS Checksum Error Checksum of CMOS is incorrect.
CP302 CMOS Setup EISA Configuration Is Not Complete - Please Run EISA Configuration Utility The slot configuration information stored in the EISA non-volatile memory is incomplete. $ Note: When either of the above EISA error messages appears, the system boots in ISA mode so that you can run the EISA Configuration Utility. Error Encountered Initializing Hard-Drive Hard drive cannot be initialized. Make sure that the adapter is installed correctly and that all cables are correctly and firmly attached.
CP302 CMOS Setup Memory Parity Error at ... Indicates a memory parity error at a specific location. You can use this location along with the memory map for your system to find and replace the bad memory chips. Memory Size Has Changed Since Last Boot Memory has been added or removed since the last boot. In EISA mode use the configuration utility to reconfigure the memory configuration. In ISA mode enter “Setup” and enter the new memory size into the memory fields. Memory Verify Error at ...
CP302 CMOS Setup Should Have EISA Board but not Found - Please Run EISA Configuration Utility The board installed is not responding to the ID request, or no board ID has been found in the indicated slot. $ Note: When this error appears, the system boots in ISA mode so that you can run the EISA configuration utility. Slot not Empty Indicates that a slot designated as empty by the EISA Configuration Utility actually contains a board.
CP302 CMOS Setup 4.14 POST Codes ISA and PCI POST codes are routed to port address 80H.
CP302 CMOS Setup Table 4-11: Normal POST Codes after System BIOS is Shadowed POST Code Action 0Bh Detects Coprocessor Initializes Power Management chipset Updates CPU microcode if P6 CPU Reads existing ESCD Scans PCI devices and busses, assigns I/O and Memory to PCI devices Initializes Clock generator Initializes Hardware monitoring / temperature sensor 0Ch Initializes keyboard buffer in BDA 0Dh 0BFh 0Dh -Program chipset Measures CPU core speed Initializes VGA video If VGA video not found: Checks f
CP302 CMOS Setup Table 4-11: Normal POST Codes after System BIOS is Shadowed POST Code Action 30h Measures total memory size 31h Initialize USB Tests all memory above 1MB, shows memory size 32h Scans for ISA PnP devices, isolates and assigns CSN to ISA PnP devices Disables SuperIO COM/LPT ports Detects and records COM/LPT ports Programs Super IO according to setup and detects any other COM/LPT ports present in the system Programs Audio system Initializes chipset EIDE channels 33h -- 34h -- 35h
CP302 CMOS Setup Table 4-11: Normal POST Codes after System BIOS is Shadowed POST Code Action 45h Initializes coprocessor 46h -- 47h Saves boot_sector_buffer 48h -- 49h -- 4Ah -- 4Bh -- 4Ch -- 4Dh -- 4Eh Checks for USB keyboard Displays previously detected POST errors. If any, checks for "Halt on" condition setting and if necessary, waits for keys "F1" or "Del".
CP302 CMOS Setup Table 4-11: Normal POST Codes after System BIOS is Shadowed POST Code Action 5Ch -- 5Dh -- 5Eh -- 5Fh -- 60h Prepares EIDE/ATAPI/SCSI for boot 61h Sets speed turbo/deturbo Final chipset initialization Final power management initialization Clears screen Shows system info 62h Programs keyboard numlock/typerate 63h Builds ESCD and saves ESCD in flash Checks for correct century in CMOS Setup timer tick in BDA Clears any pending keys in BDA Flushes cache Releases upper 32KB of
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CP302 I/O Module A Appendix I/O Module A.1 Overview ................................................................................................... A - 3 A.2 Technical Specifications ..............................................................................A - 3 A.3 Module Layouts ...........................................................................................A - 4 A.3.1 Standard I/O Module Layout .................................................................A - 4 A.3.
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CP302 I/O Module A. I/O Module A.1 Overview The PEP CP302 I/O module has been designed to provide the CP302 user with an effective gateway to the world of additional standard PC interfaces, including two COM ports, a parallel port and floppy and HardDisk interfaces. This additional capability opens up the broadest range of expansion possibilities. A.
CP302 I/O Module A.3 Module Layouts The transition modules each include additional standard PC interfaces, two configurable COM ports and one ECP/EPP compatible Parallel Port. A.3.
CP302 I/O Module A.3.2 HardDisk I/O Module Layout Serial Port COM1 (CON2) J1 33 NSR 34 Serial Port COM2 (CON6) $ ID 21112, Rev. 05 HardDisk Interface Parallel Port CON4 44 CON5 43 1 2 CON3 Floppy Interface 1 J2 Speaker Figure A-3: I/O Module Layout, HardDisk Version (Front Side) CON9 40 39 2 HARD DISK 2 1 Note: The reverse side of the HardDisk version is identical to the reverse side of the standard version illustrated above.
CP302 I/O Module A.4 Module Interfaces (Front Panel and On-board) The front panel of the I/O module is integral with the CP302 baseboard front panel please see Figure 2-2 in Chapter 2. The I/O module includes additional standard PC interfaces, two configurable COM ports, one ECP/EPP compatible Parallel Port I/O Module Connection Interface and an onboard HardDisk and floppy interface. A.4.
CP302 I/O Module Table A-3: Serial Port Connectors CON2 and CON6 Pinouts (RS422 Mode) DSUB 9 Signal Function In/Out 1 +RXD Receive data In 3 +TXD Transmit data Out 6 -RXD Inverted receive data In 8 -TXD Inverted transmit data Out 5 GND Signal ground -- 2, 4, 7 Free -- -- A.4.2 Parallel Port Interface Figure A-5: PC-compatible Parallel Interface The CP302 IO module is provided with an IEEE1284, ECP/EPPcompatible parallel port/printer interface.
CP302 I/O Module A.4.2.1 Parallel Port Connector CON4 Pinout The CP302 I/O transition module is provided with a PC-compatible 26-pin MDR connector CON4.
CP302 I/O Module A.4.3 Onboard EIDE Connector CON5 Pinout A 2.5” HardDisk may be connected directly to the CP302 I/O module. The HDD is connected to a 44-pin connector.
CP302 I/O Module Table A-5: Pinout of the AT 44-pin EIDE Connector CON5 Pin Signal Function In/Out 26 GND Ground signal -- 27 IOCHRDY I/O channel ready In 28 GND Ground signal -- 29 IDEDACKA DMA Ack Out 30 GND Ground signal -- 31 IDEIRQ Interrupt request In 32 N/C -- -- 33 A1 Address 1 Out 34 N/C -- -- 35 A0 Address 0 Out 36 A2 Address 2 Out 37 HCS0 HD select 0 Out 38 HCS1 HD select 1 Out 39 LED LED driving In 40 GND Ground signal -- 41 VCC
CP302 I/O Module A.4.4 EIDE Connector CON9 Pinout The CP302 I/O board has one EIDE interface on a standard 40-pin 2.54mm pin row connector. By means of this EIDE interface up to two HardDisk drives (one master/slave pair) may be attatched to the I/O board. The following table describes the pinout of connector CON9, with the corresponding signal names. The maximum length of cable that may be used is 35 cm.
CP302 I/O Module Table A-6: Pinout of the AT Standard EIDE Connector CON9 Pin Signal Function In/Out 24 GND Ground signal -- 25 IOR I/O read Out 26 GND Ground signal -- 27 IOCHRDY I/O channel ready In 28 GND Ground signal -- 29 IDEDACKA DMA Ack Out 30 GND Ground signal -- 31 IDEIRQ Interrupt request In 32 N/C -- -- 33 A1 Address 1 Out 34 N/C -- -- 35 A0 Address 0 Out 36 A2 Address 2 Out 37 HCS0 HD select 0 Out 38 HCS1 HD select 1 Out 39 LED
CP302 I/O Module A.4.5 Floppy Drive Interface The floppy drive interface of the CP302 I/O module is realized as a 34-pin, 2.54-mm pitch pin row connector. $ Important! If the floppy drive connection cable is inverted (pin “1” in place of pin “34”) at “power on”, the floppy drive will work uninterruptedly, with consequent risk of damaging the floppy disk inserted. A.4.5.
CP302 I/O Module A.4.6 I/O Interface Connectors (CON8 and CON10) The I/O interface connectors (CON8 and CON10) provide all the necessary signals for the CP302 I/O module. A.4.7 Speaker Connector J2 This 2-pin connector enables connection to an external speaker. A.5 Jumper Description A.5.1 Serial Port Setting The two serial ports COM1 and COM2 can be set to either RS232 or RS422 mode by setting solder jumpers. The standard configuration is RS232.
CP302 PMC and CompactPCI Expansion Module B Appendix PMC and CompactPCI Expansion Module B.1 Overview ................................................................................................... B - 3 B.2 Technical Specifications ........................................................................... B - 3 B.3 Module Layout .......................................................................................... B - 4 B.4 Module Interfaces .............................................
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CP302 PMC and CompactPCI Expansion Module B. PMC and CompactPCI Expansion Module B.1 Overview The PEP CP302 PMC module has been designed to provide the CP302 user with an effective gateway to the world of PMC modules and to the expanded capability made possible by the additional CompactPCI interface. PMC modules are renowned for their flexibility and versatility of use. They afford the user wide ranging system-independent solutions by means of easily interchanged or upgraded mezzanine add-on modules.
CP302 PMC and CompactPCI Expansion Module B.3 Module Layouts Figure B-1: PMC Module Layout, Version without CPCI Connectors (Front View) 58 CON3 57 2 PMC Interface 1 1 2 1 2 CON4 (Jn1) 63 64 63 64 CON5 (Jn2) 46 45 CON6 2 1 Figure B-2: PMC Module Layout, Version without CPCI Connectors (Rear View) 1 2 CON7 1 58 57 CON8: PCI Expansion Connector 79 80 2 1 Page B - 4 © PEP Modular Computers GmbH CON9 46 45 ID 21112, Rev. 05 Artisan Technology Group - Quality Instrumentation ..
CP302 PMC and CompactPCI Expansion Module Figure B-3: PMC Module Layout, Version with CPCI Connectors (Front View) CON3 58 57 2 PMC Interface 1 1 2 1 2 CON4 (Jn1) CON2 63 64 63 64 CON5 (Jn2) CON1 46 CON6 45 2 1 Figure B-4: PMC Module Layout, Version with CPCI Connectors (Rear View) 1 2 CON7 58 1 CON2 57 CON8: PCI Expansion Connector 79 80 CON1 2 CON9 1 ID 21112, Rev. 05 © PEP Modular Computers GmbH 46 45 Page B - 5 Artisan Technology Group - Quality Instrumentation ...
CP302 PMC and CompactPCI Expansion Module B.4 Module Interfaces B.4.1 PCI Extension Connector CON8 The PCI extension connector CON8 provides all the necessary signals for data transfer as defined by PCI Specification Rev. 2.1. B.4.2 PMC Interface The PMC interface provides an easy way to extend the CP302 via the wide array of interfaces and functions which are available on PMC modules produced by the entire range of PMC vendors.
CP302 PMC and CompactPCI Expansion Module B.4.2.
CP302 PMC and CompactPCI Expansion Module B.4.2.2 PMC Interface Jn2 (CON5) Pinout Table B-3: Jn2, 32-bit PCI Connector Pinout Pin Number Signal Name Signal Name Pin Number 1 +12V TRST# 2 3 TMS TDO 4 5 TDI Ground 6 7 Ground PCI-RSVD* 8 9 PCI-RSVD* PCI-RSVD* 10 11 BUSMODE2# +3.3V 12 13 RST# BUSMODE3# 14 15 3.3V BUSMODE4# 16 17 PCI-RSVD* Ground 18 19 AD[30] AD[29] 20 21 Ground AD[26] 22 23 AD[24] +3.3V 24 25 IDSEL AD[23] 26 27 +3.
CP302 PMC and CompactPCI Expansion Module B.4.3 CompactPCI Bus Interface B.4.3.1 CompactPCI Bus Connectors CON1 and CON2 Pinouts The CP302 PMC module is provided with two 2 mm x 2 mm pitch female CompactPCI bus connectors, J1 (CON1) and J2 (CON2). Table B-4: CompactPCI Bus Connector J1 (CON1) Pinout Pin Row A Row B Row C Row D Row E Row F 25 5V REQ64* ENUM* 3.3V 5V GND 24 AD[1] 5V V(I/O) AD[0] ACK64* GND 23 3.3V AD[4] AD[3] 5V AD[2] GND 22 AD[7] GND 3.
CP302 PMC and CompactPCI Expansion Module Table B-5: CompactPCI Bus Connector J2 (CON2) Pinout Pin Row A Row B Row C Row D Row E Row F 22 N/C N/C N/C N/C N/C GND 21 N/C GND N/C N/C N/C GND 20 N/C GND N/C GND N/C GND 19 GND GND N/C N/C N/C GND 18 N/C N/C N/C GND N/C GND 17 N/C GND N/C REQ6* GNT6* GND 16 N/C N/C N/C REQ5* GNT5* GND 15 N/C GND N/C N/C N/C GND 14 N/C N/C N/C GND N/C GND 13 N/C GND V(I/O) N/C N/C GND 12 N/C N/C N/C
CP302 PMC and CompactPCI Expansion Module B.5 Board Installation In order to keep the installation process as simple and easy as possible please follow the recommended order of work: 1. Instal the PMC module on the CP302PMC 2. Instal the package, CP302PMC plus PMC module, on the baseboard (in this case the CP302) ESD Equipment! Your carrier board and PMC module contain electrostatically sensitive devices.
CP302 PMC and CompactPCI Expansion Module Figure B-5: Installation Diagrams PMC module CP302 PMC Front Panel 2 1 CompactPCI connector PMC bezel 10mm stand-off 3 4 *M2.5 *6mm screws Page B - 12 © PEP Modular Computers GmbH ID 21112, Rev. 05 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.
CP302 IDE2 Module C Appendix IDE2 Module C.1 Overview ................................................................................................... C - 3 C.2 Technical Specifications ............................................................................. C - 3 C.3 Module Layouts .......................................................................................... C - 4 C.3.1 Standard IDE2 Module Layout............................................................. C - 4 C.3.
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CP302 IDE2 Module C. IDE2 Module C.1 Overview The PEP CP302/CP302-PM IDE2 module has been designed to provide the user with an effective gateway to the world of additional standard PC interfaces, including two COM ports, a parallel port and floppy and HardDisk interfaces. This additional capability opens up the broadest range of expansion possibilities. C.
CP302 IDE2 Module C.3 Module Layouts The transition modules each include additional standard PC interfaces, two configurable COM ports and one ECP/EPP compatible Parallel Port. C.3.
CP302 IDE2 Module C.3.
CP302 IDE2 Module C.4 Module Interfaces (Front Panel and On-board) The front panel of the IDE2 module is integral with the CP302/CP302-PM baseboard front panel - please see Figure 2-2 in Chapter 2. The IDE2 module includes additional standard PC interfaces, two configurable COM ports, one ECP/EPP compatible Parallel Port I/O Module Connection Interface and an onboard HardDisk and floppy interface. C.4.
CP302 IDE2 Module C.4.1.1 Serial Port Connectors CON2 and CON6 Pinouts The pinout of the 9-pin D-sub connectors depends on the configuration. Table C-2: Serial Port Connectors CON2 and CON6 Pinouts Pin RS232 (Standard PC) RS422 RS485 1 DCD +RXD NC 2 RXD NC NC 3 TXD +TXD +TRXD 4 DTR NC NC 5 GND GND GND 6 DSR -RXD NC 7 RTS NC NC 8 CTS -TXD -TRXD 9 RIN NC NC $ ID 21112, Rev.
CP302 IDE2 Module C.4.2 Parallel Port Interface Figure C-6: PC-Compatible Parallel Interface The IDE2 module is provided with an IEEE1284, ECP/EPP-compatible parallel port/printer interface. The parallel port is a 26-pin MDR (miniature delta ribbon) connector mounted on the front panel. To use a standard parallel port device a special adapter is necessary. 26 13 14 1 C.4.2.1 Parallel Port Connector CON4 Pinout The IDE2 module is provided with a PC-compatible 26-pin MDR connector CON4.
CP302 IDE2 Module C.4.3 EIDE Interface The EIDE interface on the IDE2 module comprises three connectors, CON5, CON7 and CON9. The CON9 connector is used to connect the IDE2 module to the baseboard, while the other two connectors, CON5 and CON7, are used to connect devices to the IDE2 module. CON5 is a 44-pin 2mm pinrow connector while CON7 is a standard 40-pin 2.54mm pinrow connector.
CP302 IDE2 Module Table C-4: Pinout of the AT 44-pin Connector Pin Signal Function In/Out 19 GND Ground signal -- 20 N/C -- -- 21 IDEDRQ DMA request In 22 GND Ground signal -- 23 IOW I/O write Out 24 GND Ground signal -- 25 IOR I/O read Out 26 GND Ground signal -- 27 IOCHRDY I/O channel ready In 28 GND Ground signal -- 29 IDEDACKA DMA Ack Out 30 GND Ground signal -- 31 IDEIRQ Interrupt request In 32 N/C -- -- 33 A1 Address 1 Out 34 N/C --
CP302 IDE2 Module C.4.3.2 EIDE Connectors CON7 and CON9 Pinouts A wide range of EIDE devices may be connected to the IDE2 module at CON7 using a ribbon cable. The following table describes the pinouts of connectors CON7 and CON9, which are identical, with the corresponding signal names..
CP302 IDE2 Module Table C-5: Pinouts of EIDE Connectors CON7 and CON9 Pin Signal Function In/Out 26 GND Ground signal -- 27 IOCHRDY I/O channel ready In 28 GND Ground signal -- 29 IDEDACKA DMA Ack Out 30 GND Ground signal -- 31 IDEIRQ Interrupt request In 32 N/C -- -- 33 A1 Address 1 Out 34 N/C -- -- 35 A0 Address 0 Out 36 A2 Address 2 Out 37 HCS0 HD select 0 Out 38 HCS1 HD select 1 Out 39 LED LED driving In 40 GND Ground signal -- Page C - 1
CP302 IDE2 Module C.4.4 Floppy Drive Interface The floppy drive interface CON3 of the IDE2 module is realized as a 34-pin, 2.54-mm pitch pin row connector. $ Important! If the floppy drive connection cable is inverted (pin “1” in place of pin “34”) at “power on”, the floppy drive will work uninterruptedly, with consequent risk of damaging the floppy disk inserted. C.4.4.
CP302 IDE2 Module C.4.5 I/O Interface Connectors (CON8 and CON10) The I/O interface connectors (CON8 and CON10) provide all the necessary signals for the IDE2 module. C.4.6 Speaker Connector J2 This 2-pin connector enables connection to an external speaker. C.5 Jumper Description C.5.1 Serial Port Setting The serial interfaces CON3 (COM1) and CON2 (COM2) on the IDE2 module may be configured for either RS232, RS422 or RS485 by setting solder jumpers.
CP302 IDE2 Module Table C-10: Jumper Setting to Configure COM2 Jumper RS232 (default) RS422 RS485 Disabled J14 Open Closed Open Open J12 Open Closed Closed Open J13 Open Closed Closed Closed J16 Open Open Closed Open J18 Open Closed Open Open The default configuration is RS232 RS422 and RS485 COM2 Termination When the IDE2 module is using the onboard RS485 interface and is the last on the RS422 or RS485 bus, then the RS422 or RS485 interface must provide termination resistan
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CP302 CP-RIO3-01 Rear I/O Module D Appendix CP-RIO3-01 Rear I/O Module D.1 Overview ..................................................................................................... D - 3 D.2 Front Panels ............................................................................................... D - 4 D.3 Module Layout: 4HP and 8HP Versions ..................................................... D - 5 D.4 Module Interfaces ....................................................................
CP302 CP-RIO3-01 Rear I/O Module CP-RIO3-01 Rear I/O Module D.5 Jumper Setting ..........................................................................................D - 14 D.5.1 COM Port Configuration .....................................................................D - 14 D.5.1.1 COM1 Configuration ....................................................................D - 14 D.5.1.2 COM2 Configuration ....................................................................D - 14 D.5.
CP302 CP-RIO3-01 Rear I/O Module D. CP-RIO3-01 Rear I/O Module D.1 Overview The CP302 family (CP302, CP302-PM and CP301) provides optional Rear I/O connectivity for peripherals, a feature which may be particularly useful in specialised CompactPCI systems. Some standard PC interfaces are implemented and assigned to the front panel and to the rear connector J2. When the Rear I/O module is used, the signals of some of the main board/front panel connectors are routed to the module interface.
CP302 CP-RIO3-01 Rear I/O Module D.2 Front Panels Note that the two green Ethernet LED’s are not active on the CP-RIO3-01. Figure D-1: CP-RIO3-01 Front Panels, 4HP and 8HP Versions 4 HP 8 HP CP RIO3-01 CP RIO3-01 ACT Page D - 4 ® PEP Modular Computers GmbH SPEED ID 21112, Rev. 05 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.
CP302 CP-RIO3-01 Rear I/O Module D.
CP302 CP-RIO3-01 Rear I/O Module D.4 Module Interfaces D.4.1 Keyboard/Mouse Interface 4 6 Figure D-4: Keyboard/Mouse Connector The PC/AT standard keyboard/mouse connector is a PS/2-type 6-pin shielded mini-DIN connector. The keyboard power supply unit is protected by a 500 mA fuse. All signal lines are EMI-filtered. 2 1 5 3 A special adapter to connect a mouse device and/or a keyboard to the PS/2 connector ia available from PEP D.4.1.
CP302 CP-RIO3-01 Rear I/O Module D.4.2 USB Interfaces Figure D-5: USB Connector CON4 There are two identical USB interfaces on the CP-RIO3-01 module (8HP version) each with a maximum transfer rate of 12 Mbit provided for connecting USB devices. One USB peripheral may be connected to each port. To connect more than two USB devices an external hub is required. 1 2 3 4 5 6 7 8 D.4.2.
CP302 CP-RIO3-01 Rear I/O Module D.4.3 VGA Interface Figure D-6: D-sub VGA Connector 10 15 5 11 1 6 D.4.3.1 VGA Connector CON5 Pinout The 15-pin female connector CON5 is used to connect a VGA monitor to the CP-RIO3-01 (8HP version) board. Table D-3: VGA Connector CON5 Pinout D-sub 15 Signal Function In/Out 1 Red Red video signal output Out 2 Green Green video signal output Out 3 Blue Blue video signal output Out 13 Hsync Horizontal sync. TTL out 14 Vsync Vertical sync.
CP302 CP-RIO3-01 Rear I/O Module D.4.4 Fast Ethernet Interface Figure D-7: Ethernet/Fast Ethernet Connector 1 The Ethernet connector is realized as an RJ45 twisted-pair connector. The interface provides automatic detection and switching between 10Base-T and 100Base-TX data transmission. 8 D.4.4.1 RJ45 Connector CON2 Pinout CON2 supplies the 10Base-TX/100Base-TX interface to the Ethernet controller.
CP302 CP-RIO3-01 Rear I/O Module D.4.6 Serial Port Interfaces Figure D-8: PC-compatible D-sub Serial Interface 6 1 9 5 D.4.6.1 Serial Port Connectors CON8 and CON10 Pinouts The serial port male connectors CON2 and CON6 allow the connection of RS232 devices to the CP-RIO3-01 board.
CP302 CP-RIO3-01 Rear I/O Module D.4.7 Fan Control Interface (optional) A fan for CPU cooling can be connected via the power connector CON9. D4.7.1 Fan Control Connector CON9 Pinout Table D-6: Fan Control Connector CON9 Pinout Pin Function 1 Ground 2 5V Fan Supply Voltage at a maximum current of 300 mA 3 Fansense D.4.8 EIDE Interface D.4.8.
CP302 CP-RIO3-01 Rear I/O Module Table D-7: Pinout of AT Standard Connector EIDE2 Pin Signal Function In/Out 14 HD13 HD data 13 In/Out 15 HD1 HD data 1 In/Out 16 HD14 HD data 14 In/Out 17 HD0 HD data 0 In/Out 18 HD15 HD data 15 In/Out 19 GND Ground signal -- 20 N/C -- -- 21 IDEDRQ DMA request In 22 GND Ground signal -- 23 IOW I/O write Out 24 GND Ground signal -- 25 IOR I/O read Out 26 GND Ground signal -- 27 IOCHRDY I/O channel ready In 28 GND
CP302 CP-RIO3-01 Rear I/O Module D.4.9 Rear I/O interface on Compact PCI Connector CON1 The CP-RIO3-01 conducts a wide range of I/O signals through the Rear I/O connector J2. $ Note: If the Rear I/O feature is selected the PCI interface is only 32-bit. For the 3U Rear I/O a special backplane is necessary. D.4.9.
CP302 CP-RIO3-01 Rear I/O Module Legend for table on preceding page: 1) Ethernet, SMBUS, Keyboard, Mouse, USB and Power (64-bit and Rear I/O possible) 2) COM1, COM2 (only 32-bit and Rear I/O) 3) VGA Signals (only 32-bit and Rear I/O) 4) EIDE Port (only 32-bit and Rear I/O) 5) Reserved 6) The battery and LED signals are active only on the CP301 and CP302-PM The greyed table cells indicate the power grouping D5 Jumper Setting D.5.
CP302 CP-RIO3-01 Rear I/O Module D.5.2 Shorting Chassis GND (Shield) to Logic GND The front panel including the front panel connectors are isolated to the logic ground. This zero Ohm resistor enables connection between the chassis GND and logic GND. Table D-11: Shorting Chassis GND (Shield) to Logic GND R36 Function Open Connectors are isolated to logic GND Short Connectors are connected to logic GND and chassis GND The default setting is indicated by italics. ID 21112, Rev.
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