Specifications
CP302 CMOS Setup
ID 21112, Rev. 05 Page 4 - 19® PEP Modular Computers GmbH
SDRAM RAS Precharge Time
The precharge time is the number of cycles it takes for the RAS to accumulate its
charge before DRAM refresh. If insufficient time is allowed, refresh may be incomplete
and the DRAM may fail to retain data.
SDRAM CAS Latency Time
When synchronous DRAM is installed, you can control the number of CLK’s between
the SDRAM’s sample of a read command and the time when the controller samples
read data from the SDRAM’s. Do not reset this field from the default value specified by
the system designer.
SDRAM Precharge Control
When Enabled, all CPU cycles to SDRAM result in an All Banks Precharge Command
on the SDRAM interface.
DRAM Data Integrity Mode
Select Non-ECC or ECC (error-correcting code), according to the type of installed
DRAM.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at 0xF0000 to 0xFFFFF,
resulting in better system performance. However, if any program writes to this memory
area, a memory access error may result.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at 0xC0000 to 0xC7FFF,
resulting in better video performance. However, if any program writes to this memory
area, a memory access error may result.
Video RAM Cacheable
Selecting Enabled allows caching of the video memory (RAM) at 0xA0000 to 0xAFFFF,
resulting in better video performance. However, if any program writes to this memory
area, a memory access error may result.
8/16-bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles between PCI-originated I/O cycles
to the ISA bus. This delay takes place because the PCI bus is so much faster than the
ISA bus.
These two fields let you add recovery time (in bus clock cycles) for 16-bit and 8-bit I/O.
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adaptor ROM. When this area is
reserved, it cannot be cached. The user information for peripherals that need to use this
area of system memory usually discusses their memory requirements.
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