Specifications

ASIX ELECTRONICS CORPORATION
29
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
7.0 Embedded Ethernet Phy Register Description
Address Register Name Description
0h BMCR Basic mode control register, basic register.
1h BMSR Basic mode status register, basic register.
2h PHYIDR1 PHY identifier register 1, extended register.
3h PHYIDR2 PHY identifier register 2, extended register.
4h ANAR Auto negotiation advertisement register, extended register.
5h ANLPAR Auto negotiation link partner ability register, extended register.
6h ANER Auto negotiation expansion register, extended register.
7h Reserved Reserved and currently not supported.
8h-Fh IEEE reserved IEEE 802.3u reserved.
Table 6: Embedded Ethernet Phy Register Map
7.1 Detailed Register Description
The following abbreviations apply to following sections for detailed register description.
Reset value:
1: Bit set to logic one
0: Bit set to logic zero
X: No set value
Pin#: Value latched from pin # at reset time
Access type:
RO: Read only
RW: Read or write
Attribute:
SC: Self-clearing
PS: Value is permanently set
LL: Latch low
LH: Latch high
7.1.1 Basic Mode Control Register (BMCR)
Address 00h
Bit Bit Name Default Description
15 Reset 0, RW / SC Reset:
1 = Software reset
0 = Normal operation
14 Loopback 0, RW Loopback:
1 = Loopback enabled
0 = Normal operation
13 Speed selection 1, RW Speed selection:
1 = 100 Mb/s
0 = 10 Mb/s
12 Auto-negotiation
enable
1, RW Auto-negotiation enable:
1 = Auto-negotiation enabled. Bits 8 and 13 of this register are
ignored when this bit is set.
0 = Auto-negotiation disabled. Bits 8 and 13 of this register
determine the link speed and mode.
11 Power down 0, RW Power down: