Specifications

ASIX ELECTRONICS CORPORATION
37
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
8.4.2 Reset Timing
XIN12M
RESET_N
Symbol Description Min Typ Max Units
Trst Reset pulse width (6ms ~10ms) after XIN12M
is running
72000 - - XIN12M clock cycle
8.4.3 MII Timing (100Mbps)
Ttclk Ttch Ttcl
TX_CLK
Tts Tth
TXD [3:0]
TX_EN, TX_ER
Symbol Description Min Typ Max Units
Ttclk TX_CLK clock cycle time *1
- 40.0 - ns
Ttch TX_CLK clock high time *2
- 20.0 - ns
Ttcl TX_CLK clock low time *2
- 20.0 - ns
Tts TXD [3:0], TX_EN, TX_ER setup time
28.0 - - ns
Tth TXD [3:0], TX_EN, TX_ER hold time
5.0 - - ns
Trclk Trch Trcl
RX_CLK
Trs Trh
RXD [3:0]
RX_DV, RX_ER
Symbol Description Min Typ Max Units
Trclk RX_CLK clock cycle time *1
- 40.0 - ns
Trch RX_CLK clock high time *2
- 20.0 - ns
Trcl RX_CLK clock low time *2
- 20.0 - ns
Trs RXD [3:0], RX_DV, and RX_ER setup time
3.0 - - ns
Trh RXD [3:0], RX_DV, and RX_ER hold time
0.5 - - ns
*1: For 10Mbps, the typical value of Ttclk and Trclk shall scale to 400ns.
*2: For 10Mbps, the typical value of Ttch, Ttcl, Trch, and Trcl shall scale to 200ns.
Trs
t