User Manual
Table Of Contents
- Chapter 1 Introduction
- 1.1 Package Contents
- Chapter 2 Installation
- 2.1 Installing the CPU
- 2.2 Installing the CPU Fan and Heatsink
- 2.3 Installing Memory Modules (DIMM)
- 2.4 Expansion Slots (PCI and PCI Express Slots)
- 2.5 Jumpers Setup
- 2.6 Onboard Headers and Connectors
- 2.7 CrossFireXTM and Quad CrossFireXTM Operation Guide
- 2.7.1 Installing Two CrossFireXTM-Ready Graphics Cards
- 2.7.2 Driver Installation and Setup
- 2.8 M.2_SSD (NGFF) Module Installation Guide
- Chapter 3 Software and Utilities Operation
56
English
CPU Conguration
Multi Core Enhancement
Improve the system's performance by forcing the CPU to perform the highest
frequency on all CPU cores simultaneously. Disable to reduce power consumption .
CPU Ratio
e CPU speed is determined by the CPU Ratio multiplied with the BCLK.
Increasing the CPU Ratio will increase the internal CPU clock speed without
aecting the clock speed of other components.
CPU Cache Ratio
e CPU Internal Bus Speed Ratio. e maximum should be the same as the CPU
Ratio.
Minimum CPU Cache Ratio
Set the minimum CPU Internal Bus Speed Ratio.
BCLK Frequency
e CPU speed is determined by the CPU Ratio multiplied with the BCLK.
Increasing the BCLK will increase the internal CPU clock speed but also aect the
clock speed of other components.
Boot Performance Mode
Default is Max Non-Turbo performance mode. It will keep cpu Flex-ratio till OS
hando. Max Battery mode will set CPU ratio as x8 till OS hando. is option is
suggested for BCLK overclocking.
FCLK Frequency
Congure the FCLK Frequency.
Intel SpeedStep Technology
Intel SpeedStep technology allows processors to switch between multiple frequen-
cies and voltage points for better power saving and heat dissipation.
Intel Turbo Boost Technology
Intel Turbo Boost Technology enables the processor to run above its base operating
frequency when the operating system requests the highest performance state.
Intel Speed Shift Technology
Enable/Disable Intel Speed Shi Technology support. Enabling will expose the
CPPC v2 interface to allow for hardware controlled P-sates.