User Manual
Table Of Contents
- Chapter 1 Introduction
- 1.1 Package Contents
- Chapter 2 Installation
- 2.1 Installing the CPU
- 2.2 Installing the CPU Fan and Heatsink
- 2.3 Installing Memory Modules (DIMM)
- 2.4 Expansion Slots (PCI and PCI Express Slots)
- 2.5 Jumpers Setup
- 2.6 Onboard Headers and Connectors
- 2.7 CrossFireXTM and Quad CrossFireXTM Operation Guide
- 2.7.1 Installing Two CrossFireXTM-Ready Graphics Cards
- 2.7.2 Driver Installation and Setup
- 2.8 M.2_SSD (NGFF) Module Installation Guide
- Chapter 3 Software and Utilities Operation
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English
a row of memory and accessing columns within it.
Row Precharge: e number of clock cycles required between the issuing of the
precharge command and opening the next row.
RAS# Active Time (tRAS)
e number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
e delay between when a memory chip is selected and when the rst active command can
be issued.
Secondary Timing
Write Recovery Time (tWR)
e amount of delay that must elapse aer the completion of a valid write operation,
before an active bank can be precharged.
Refresh Cycle Time (tRFC)
e number of clocks from a Refresh command until the rst Activate command to
the same rank.
RAS to RAS Delay (tRRD_L)
e number of clocks between two rows activated in dierent banks of the same
rank.
RAS to RAS Delay (tRRD_S)
e number of clocks between two rows activated in dierent banks of the same
rank.
Write to Read Delay (tWTR_L)
e number of clocks between the last valid write operation and the next read command to
the same internal bank.
Write to Read Delay (tWTR_S)
e number of clocks between the last valid write operation and the next read command to
the same internal bank.
Read to Precharge (tRTP)
e number of clocks that are inserted between a read command to a row pre-
charge command to the same rank.