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Z390 Taichi Ultimate
e number of clocks between two rows activated in dierent banks of the same
rank.
Write to Read Delay (tWTR_L)
e number of clocks between the last valid write operation and the next read command to
the same internal bank.
Write to Read Delay (tWTR_S)
e number of clocks between the last valid write operation and the next read command to
the same internal bank.
Read to Precharge (tRTP)
e number of clocks that are inserted between a read command to a row pre-
charge command to the same rank.
Four Activate Window (tFAW)
e time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Congure CAS Write Latency.
Third Timing
tREFI
Congure refresh cycles at an average periodic interval.
tCKE
Congure the period of time the DDR4 initiates a minimum of one refresh
command internally once it enters Self-Refresh mode.
Turn Around Timing
tRDRD_sg
Congure between module read to read delay.
tRDRD_dg
Congure between module read to read delay.
tRDRD_dr
Congure between module read to read delay.