User's Manual

第二章：BIOS 信息2-14
DRAM CKE Minimum pulse width [Auto]
設置值有：[Auto] [4 DRAM Clock] – [15 DRAM Clock]
DRAM CAS# Write to Latency [Auto]
設置值有：[Auto] [1 DRAM Clock] – [15 DRAM Clock]
DRAM RTL (CHA) [Auto]
設置值有：[Auto] [1 DRAM Clock] – [63 DRAM Clock]
DRAM RTL (CHB) [Auto]
設置值有：[Auto] [1 DRAM Clock] – [63 DRAM Clock]
DRAM I0-L (CHA) [Auto]
設置值有：[Auto] [Delay 1 Clock] - [Delay 15 Clock]
DRAM IO-L (CHB) [Auto]
設置值有：[Auto] [Delay 1 Clock] - [Delay 15 Clock]
Third Timings
tWRDR (DD) [Auto]
設置值有：[Auto] [1 DRAM Clock] – [8 DRAM Clock]
tRWDR (DD) [Auto]
設置值有：[Auto] [1 DRAM Clock] – [8 DRAM Clock]
tRWSR [Auto]
設置值有：[Auto] [1 DRAM Clock] – [8 DRAM Clock]
tRR (DD) [Auto]
設置值有：[Auto] [1 DRAM Clock] – [8 DRAM Clock]
tRR (DR) [Auto]
設置值有：[Auto] [1 DRAM Clock] – [8 DRAM Clock]
tRRSR [Auto]
設置值有：[Auto] [4 DRAM Clock] – [7 DRAM Clock]
tWW (DD) [Auto]
設置值有：[Auto] [1 DRAM Clock] – [8 DRAM Clock]
tWW (DR) [Auto]
設置值有：[Auto] [1 DRAM Clock] – [8 DRAM Clock]
tWWSR [Auto]
設置值有：[Auto] [4 DRAM Clock] – [7 DRAM Clock]