User Manual

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PRIME / ProArt / TUF GAMING Intel 700 Series BIOS マ
DQ RTT PARK
設定オ: [Auto] [0 DRAM Clock] [34 DRAM Clock] [40 DRAM Clock]
[48 DRAM Clock] [60 DRAM Clock] [80 DRAM Clock] [120 DRAM Clock] [240
DRAM Clock]
DQ RTT PARK DQS
設定オ: [Auto] [0 DRAM Clock] [34 DRAM Clock] [40 DRAM Clock]
[48 DRAM Clock] [60 DRAM Clock] [80 DRAM Clock] [120 DRAM Clock] [240
DRAM Clock]
GroupA CA ODT
設定オ: [Auto] [0 DRAM Clock] [40 DRAM Clock] [60 DRAM Clock]
[80 DRAM Clock] [120 DRAM Clock] [240 DRAM Clock] [480 DRAM Clock]
GroupA CS ODT
設定オ: [Auto] [0 DRAM Clock] [40 DRAM Clock] [60 DRAM Clock]
[80 DRAM Clock] [120 DRAM Clock] [240 DRAM Clock] [480 DRAM Clock]
GroupA CK ODT
設定オ: [Auto] [0 DRAM Clock] [40 DRAM Clock] [60 DRAM Clock]
[80 DRAM Clock] [120 DRAM Clock] [240 DRAM Clock] [480 DRAM Clock]
GroupB CA ODT
設定オ: [Auto] [0 DRAM Clock] [40 DRAM Clock] [60 DRAM Clock]
[80 DRAM Clock] [120 DRAM Clock] [240 DRAM Clock] [480 DRAM Clock]
GroupB CS ODT
設定オ: [Auto] [0 DRAM Clock] [40 DRAM Clock] [60 DRAM Clock]
[80 DRAM Clock] [120 DRAM Clock] [240 DRAM Clock] [480 DRAM Clock]
GroupB CK ODT
設定オ: [Auto] [0 DRAM Clock] [40 DRAM Clock] [60 DRAM Clock]
[80 DRAM Clock] [120 DRAM Clock] [240 DRAM Clock] [480 DRAM Clock]
Pull-up Output Driver Impedance
設定オ: [Auto] [34 DRAM Clock] [40 DRAM Clock] [48 DRAM Clock]
Pull-Down Output Driver Impedance
設定オ: [Auto] [34 DRAM Clock] [40 DRAM Clock] [48 DRAM Clock]
RTL IOL Control
Round Trip Latency Init Value MC0-1 CHA-B
設定オ: [Auto] [0] - [255]
Round Trip Latency Max Value MC0-1 CHA-B
設定オ: [Auto] [0] - [255]
Round Trip Latency O󱐯set Value Mode Sign MC0-1 CHA-B
設定オ: [-] [+]
Round Trip Latency O󱐯set Value MC0-1 CHA-B
設定オ: [Auto] [0] - [255]
Round Trip Latency MC0-1 CHA-B R0-7
設定オ: [Auto] [0] - [255]
Memory Training Algorithms
さまざまなニングアルゴリムの/します
Early Command Training
ョン: [Auto] [Enabled] [Disabled]
SenseAmp O󱐯set Training
ョン: [Auto] [Enabled] [Disabled]