User's Manual

2-182-18
2-182-18
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Chapter 2: Hardware informationChapter 2: Hardware information
Chapter 2: Hardware informationChapter 2: Hardware information
Chapter 2: Hardware information
2.4.32.4.3
2.4.32.4.3
2.4.3
Memory mirroring and sparing technologyMemory mirroring and sparing technology
Memory mirroring and sparing technologyMemory mirroring and sparing technology
Memory mirroring and sparing technology
The Intel 5000P chipset supports the memory mirroring and sparing
technology. Refer to the below sections:
Memory Mirroring:Memory Mirroring:
Memory Mirroring:Memory Mirroring:
Memory Mirroring:
When enabling memory mirroring function in the BIOS setting (please refer
the
chapter 4.4.2 Chipset Configuration and configure thechapter 4.4.2 Chipset Configuration and configure the
chapter 4.4.2 Chipset Configuration and configure thechapter 4.4.2 Chipset Configuration and configure the
chapter 4.4.2 Chipset Configuration and configure the
option “Memory Branch Mode” as Mirror)option “Memory Branch Mode” as Mirror)
option “Memory Branch Mode” as Mirror)option “Memory Branch Mode” as Mirror)
option “Memory Branch Mode” as Mirror), Branch 1 contains a
replicate copy of the data in Branch 0. The DIMMs must cover the same
slot position on both branches. DIMMs that cover a slot position must be
identical with respect to size, speed, and organization. DIMMs within a slot
position must match each other, but aren’t required to match adjacent slot
positions.
And the total memories size will be the half of all installedAnd the total memories size will be the half of all installed
And the total memories size will be the half of all installedAnd the total memories size will be the half of all installed
And the total memories size will be the half of all installed
memories.memories.
memories.memories.
memories.
The below two memory configurations were required to operate in mirrored
mode.
1. Configuration 1 (Mirroring):
Four memories population Four memories population
Four memories population Four memories population
Four memories population
DIMM 00 (Slot 0:Channel 0)DIMM 00 (Slot 0:Channel 0)
DIMM 00 (Slot 0:Channel 0)DIMM 00 (Slot 0:Channel 0)
DIMM 00 (Slot 0:Channel 0)
MCHMCH
MCHMCH
MCH
Branch 0Branch 0
Branch 0Branch 0
Branch 0
DIMM 01 (Slot 1:Channel 0)DIMM 01 (Slot 1:Channel 0)
DIMM 01 (Slot 1:Channel 0)DIMM 01 (Slot 1:Channel 0)
DIMM 01 (Slot 1:Channel 0)
DIMM 10 (Slot 0:Channel 1)DIMM 10 (Slot 0:Channel 1)
DIMM 10 (Slot 0:Channel 1)DIMM 10 (Slot 0:Channel 1)
DIMM 10 (Slot 0:Channel 1)
DIMM 11 (Slot 0:Channel 1)DIMM 11 (Slot 0:Channel 1)
DIMM 11 (Slot 0:Channel 1)DIMM 11 (Slot 0:Channel 1)
DIMM 11 (Slot 0:Channel 1)
DIMM 20 (Slot 0:Channel 2)DIMM 20 (Slot 0:Channel 2)
DIMM 20 (Slot 0:Channel 2)DIMM 20 (Slot 0:Channel 2)
DIMM 20 (Slot 0:Channel 2)
DIMM 21 (Slot 0:Channel 2)DIMM 21 (Slot 0:Channel 2)
DIMM 21 (Slot 0:Channel 2)DIMM 21 (Slot 0:Channel 2)
DIMM 21 (Slot 0:Channel 2)
DIMM 30 (Slot 0:Channel 3)DIMM 30 (Slot 0:Channel 3)
DIMM 30 (Slot 0:Channel 3)DIMM 30 (Slot 0:Channel 3)
DIMM 30 (Slot 0:Channel 3)
DIMM 31 (Slot 0:Channel 3)DIMM 31 (Slot 0:Channel 3)
DIMM 31 (Slot 0:Channel 3)DIMM 31 (Slot 0:Channel 3)
DIMM 31 (Slot 0:Channel 3)
Branch 1Branch 1
Branch 1Branch 1
Branch 1
(Mirror)(Mirror)
(Mirror)(Mirror)
(Mirror)