User Manual

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Memory RAS Configuration
Displays and provides options to change the memory RAS Settings.
Dynamic ECC Mode Selection [Enabled]
Allows you to enable or disable dynamic ECC mode selection.
Configuration options: [Disabled] [Enabled] [Enable + Allow Partial Poison Mode]
Enable Pcode WA
for SAI PG [Disabled]
Allows you to enable or disable Pcode Work Around for SAI Policy group for A Step.
Configuration options: [Disabled] [Enabled]
Memory Bank Sparing [Disabled]
Allows you to enable or disable Memory Bank Sparing. This feature is only available
for HBM.
Configuration options: [Disabled] [Enabled]
Memory Correctable Error Flood Policy [Frequency]
[Disable]
Don’t deal with Memory CE flood
[Once] Only First Memory CE will trigger SMI, and BIOS will disable this rank
silicon side to trigger SMI.
[Frequency] Disable SMI when Memory CE reaches threshold within time limits.
Correctable Error Threshold [7FFF]
Allows you to set the Correctable Error Threshold (0x01 - 0x7FFF) used for DDR
sparing and DDR leaky bucket.
Configuration options: [1] - [7FFF]
Trigger SW Error Threshold [Disabled]
Allows you to enable to disable sparing trigger SW error match threshold.
Configuration options: [Disabled] [Enabled]
Leaky bucket time window based interface [Disabled]
Allows you to enable to disable leaky bucket time window based interface for DDR.
Configuration options: [Disabled] [Enabled]
The following item appears only when Leaky bucket time window based interface is set
to [Enabled].
Leaky bucket time window based interface Hour [24]
Allows you to set the leaky bucket time window based interface Hour used
for DDR.
Configuration options: [0] - [24]
Leaky bucket time window based interface Minute [0]
Allows you to set the leaky bucket time window based interface Minute
used for DDR.
Configuration options: [0] - [60]
Partial Cache Line Sparing PCLS [Enabled]
Allows you to enable or disable PCLS Sparing.
Configuration options: [Disabled] [Enabled]