User Manual
Table Of Contents
- Safety information
- Chapter 1: Product Introduction
- Chapter 2: Hardware Information
- 2.1 Chassis cover
- 2.2 Air duct
- 2.3 Central Processing Unit (CPU)
- 2.4 System memory
- 2.5 Storage devices
- 2.5.1 Installing an E1.S module (optional)
- 2.5.2 Removing an E1.S module (optional)
- 2.5.3 Installing an external 2.5” storage device (on selected models)
- 2.5.4 Removing an external 2.5” storage device (on selected models)
- 2.5.5 Installing an internal 2.5” storage device (optional on selected models)
- 2.5.6 Removing an internal 2.5” storage device (optional on selected models)
- 2.6 Expansion slot
- 2.7 Cable connections
- 2.8 Removable/optional components
- 2.9 Rail Kit Options
- Chapter 3: Motherboard Information
- Chapter 4: BIOS Setup
- 4.1 Managing and updating your BIOS
- 4.2 BIOS setup program
- 4.3 Main menu
- 4.4 Performance Tuning menu
- 4.5 Advanced menu
- 4.5.1 Trusted Computing
- 4.5.2 ACPI Settings
- 4.5.3 Redfish Host Interface Settings
- 4.5.4 Onboard LAN Configuration
- 4.5.5 UEFI Variables Protection
- 4.5.6 Serial Port Console Redirection
- 4.5.7 SIO Configuration
- 4.5.8 PCI Subsystem Settings
- 4.5.9 USB Configuration
- 4.5.10` Network Stack Configuration
- 4.5.11 NVMe Configuration
- 4.5.12 APM Configuration
- 4.5.13 Tls Auth Configuration
- 4.5.14 Intel(R) Virtual RAID on CPU
- 4.5.15 Third-party UEFI driver configurations
- 4.6 Platform Configuration menu
- 4.7 Socket Configuration menu
- 4.8 Security menu
- 4.9 Boot menu
- 4.10 Tool menu
- 4.11 Event Logs menu
- 4.12 Server Mgmt menu
- 4.13 Exit menu
- Appendix
1-14
1.7.4 Q-Code table
Action PHASE POST CODE TYPE DESCRIPTION
SEC Start
up
Security Phase
0x01 Progress Power on post code
0x02 Progress Load BSP microcode
0x03 Progress Perform early platform cache Initialization
0x04 Progress Set cache as ram for PEI phase
0x05 Progress Establish Stack
0x06 Progress CPU Early Initialization
Quick VGA
PEI(Pre-EFI
initialization)
phase
0x10
Progress
PEI Core Entry
0x11 PEI cache as ram CPU initial
0x15 NB Initialization before installed memory
0x19 SB Initialization before installed memory
VR initialization
0xC8
Progress
Infineon Address
0xCC
0xD4
Ti Address
0xDC
0xB8
0xBC
0xB0
0xB4
OCMR initialization
0x11
Progress
Enter OCMR Procedures
0x12 Enter OCMR On S3
0x13 Check New CPU
0x14 Check Cmos Fail
0x16 Check Overclock Fail
0x18 Prepare Parameters
0x21 Build Voltage Table
0x22 Patch Voltage Table
0x23 Adjust Voltage Table
0x24 Before Set Voltages
0x25 Set Voltages
0x31 Before Set Spread Spectrum
0x32 SetBclkStrapAndFrequencyPei
0x33 Set Spread Spectrum
0x34 After Set Frequency
KTI initialization
0xA0
Progress
Initialize KTI input structure
0xA1 Collect info such as SBSP, Boot Mode, Reset type
0xA3 Setup up minimum path between SBSP & other sockets
0xA6 Sync up with PBSPs
0xA7 Topology discovery and route calculation
0xA8 Program final route
0xA9 Program final IO SAD setting
0xAA Protocol layer and other Uncore settings
0xAB Transition links to full speed opeartion
0xAE Coherency Settings
0xAF KTI Complete
IIO Early
initialization
0xE0
Progress
IIO early init
0xE1 Early Pre-link training setting
0xE2 IIO Gen3 EQ programming
0xE3 IIO Link training
0xE4 IIO Gen3 override
0xE5 IIO early init exit
0xE6 IIO late init
0xE7 PCIE port init
0xE8 IOAPIC init
0xE9 VTD init
0xEA IOAT init
0xEB IIO DFX init
0xEC NTB init
0xED Security init
0xEE IIO late init exit
0xEF IIO On ready to boot
(continued on the next page)