User Manual
Table Of Contents
- Safety information
- Chapter 1: Product Introduction
- Chapter 2: Hardware Setup
- 2.1 Chassis cover
- 2.2 Air ducts
- 2.3 Central Processing Unit (CPU)
- 2.4 System memory
- 2.5 Storage devices
- 2.6 Expansion slots
- 2.6.1 Installing an expansion card to the front PCIe expansion card bracket (on select models)
- 2.6.2 Installing an ASUS PIKE II or RAID card
- 2.6.3 Installing the Cache Vault Power Module
- 2.6.4 Installing an expansion card to the rear PCIe expansion card slots (on select models)
- 2.6.5 Installing an OCP 3.0 card to the rear OCP 3.0 socket board (on select models)
- 2.6.6 (optional) Installing the PFR module
- 2.7 Cable connections
- 2.8 Removable/optional components
- 2.9 Rail kit options
- Chapter 3: Motherboard Information
- Chapter 4: BIOS Setup
- 4.1 Managing and updating your BIOS
- 4.2 BIOS setup program
- 4.3 Main menu
- 4.4 Performance Tuning menu
- 4.5 Advanced menu
- 4.5.1 Trusted Computing
- 4.5.2 ACPI Settings
- 4.5.3 Redfish Host Interface Settings
- 4.5.4 Onboard LAN Configuration
- 4.5.5 Serial Port Console Redirection
- 4.5.6 SIO Configuration
- 4.5.7 PCI Subsystem Settings
- 4.5.8 USB Configuration
- 4.5.9 Network Stack Configuration
- 4.5.10 NVMe Configuration
- 4.5.11 APM Configuration
- 4.5.12 T1s Auth Configuration
- 4.5.13 Third-party UEFI driver configurations
- 4.6 Platform Configuration menu
- 4.7 Socket Configuration menu
- 4.8 Security menu
- 4.9 Boot menu
- 4.10 Tool menu
- 4.11 Event Logs menu
- 4.12 Server Mgmt menu
- 4.13 Save & Exit menu
- Chapter 5: RAID Configuration
- Appendix
A-2
Appendix
Block diagram
CPU1
EGS
Up to TDP 350W
80 Lanes
CPU2
EGS
Up to TDP 350W
80 Lanes
UPI
UPI
UPI
UPI
DMI3 x4
Up to 4800 (2DPC)
DDR5
DDR5
DDR5
DDR5
DDR5
DDR5
DDR5
DDR5
Up to 4800 (2DPC)
DDR5
DDR5
DDR5
DDR5
DDR5
DDR5
DDR5
DDR5
x16 Gen5
PCIe G5 x16 (GPU4)
PCIe G5 x16 (GPU3)
PCIe G5 x16 (NIC 02)
x8 Gen5
x8 Gen5
NVMe 1/2 Riser x8 (Optional)
NVMe 3/4 Riser x8 (Optional)
BMC AST2600
Emmitsburg
PCH
PCIe G5 x16
Front PCIe Riser (for HBA card)
or
Front 4* NVMe support (Optional)
x16 Gen5
x16 Gen5
x16 Gen5
x16 Gen5
LAN 1GbE or 10GbE
Sys Fan x 6
GPU Fan x 5
RGMII
Fan Control
Fan Control
SPI MUX
SPI MUX
SPI
eSPI
SPI
x8 Gen5
x8 Gen5
NVMe 5/6 Riser x8 (Optional)
NVMe 7/8 Riser x8 (Optional)
PCIe G5 x16
Front PCIe Riser (for HBA card)
or
Real -OCP 3.0 (Optional)
x16 Gen5
PCIe
Switch
x16 Gen5
PCIe G5 x16 (GPU1)
PCIe G5 x16 (GPU2)
PCIe G5 x16 (NIC 01)
x16 Gen5
x16 Gen5
x16 Gen5
Gen2 x1
SATA III
USB 2.0
SPI
SPI
PCIe
Switch
x16 Gen5
PCIe G5 x16 (GPU6)
PCIe G5 x16 (GPU5)
PCIe G5 x16 (NIC 03)
x16 Gen5
x16 Gen5
x16 Gen5
PCIe
Switch
x16 Gen5
PCIe G5 x16 (GPU7)
PCIe G5 x16 (GPU8)
PCIe G5 x16 (NIC 04)
x16 Gen5
x16 Gen5
x16 Gen5
PCIe
Switch
Super IOCOM
BMC FW A
BIOS A TPMROT Module
BACK IO Board
SATA Port x8
USB 2.0
Front IO Board
USB 2.0 Port x 1
USB 3.0
Front IO Board
USB 3.0 Port x 1
x4 Gen 3
Lan Card
SlimSAS x4
x4 Gen 3
M.2 Card
SlimSAS x4
Q-Code table
(continued on the next page)
ACTION PHASE POST CODE TYPE DESCRIPTION
Normal boot
Security Phase
01 Progress First post code(POWER_ON_POST_CODE)
02 Progress Load BSP microcode(MICROCODE_POST_CODE)
03 Progress Set cache as ram for PEI phase(CACHE_ENABLED_POST_CODE)
06 Progress CPU Early init.(CPU_EARLY_INIT_POST_CODE)
04 Progress initializes South bridge for PEI preparation
PEI(Pre-EFI
initialization) phase
10 Progress PEI Core Entry
15 Progress NB initialize before installed memory
19 Progress SB initialize before installed memory
78~00 Progress Wait BMC ready(duration: 120 seconds).
A1 MRC Progress QPI initialization
A3 MRC Progress QPI initialization
A7 MRC Progress QPI initialization
A8 MRC Progress QPI initialization
A9 MRC Progress QPI initialization
AA MRC Progress QPI initialization
AB MRC Progress QPI initialization
AC MRC Progress QPI initialization
AD MRC Progress QPI initialization
AE MRC Progress QPI initialization
AF MRC Progress QPI initialization Complete
2F Progress Memory Init.
B0 MRC Progress Memory Init.
B1 MRC Progress Memory Init.
AF MRC Progress RC Reset if require
B4 MRC Progress Memory Init.
B2 MRC Progress Memory Init.
B3 MRC Progress Memory Init.
B5 MRC Progress Memory Init.
B6 MRC Progress Memory Init.
B7 MRC Progress Memory Init.
B8 MRC Progress Memory Init.
B9 MRC Progress Memory Init.
BA MRC Progress Memory Init.