User's Manual

Intel
®
820 Chipset Design Guide 4-1
Clocking
Clocking
4
4.1 Clock Generation
There are two clock generator components required in an Intel
®
820 chipset based system. The
Direct Rambus
*
Clock Generator (DRCG) generates clock for the Direct Rambus
*
interface while
the CK133 component generates clocks for the rest of the system. Clock synthesizers that meet the
Intel CK98 Clock Specification are suitable for an Intel
®
820 chipset based system. The CK133
generates the clocks listed in Table 4-1.
The CK133 is a mixed voltage component. Some of the output clocks are 3.3V and some of the
output clock are 2.5V. As a result, the CK133 device requires both 3.3V and 2.5V. These power
supplies should be a clean as possible. Noise in the power delivery system for the clock driver can
cause noise on the clock lines.
The MCH uses the same clock for hub interface and AGP. It is important that the
hub interface/AGP clocks are routed to ensure the skew requirements are met between:
•
The MCH hub interface/AGP clock and the AGP connector (or device)
Table 4-1. Intel
®
820 Chipset Platform System Clocks
Number
Name on
CK133
Used for Routed to
Name on
Receiver
Frequency Voltage
4 CPUCLK[0-3] System Bus Clock
2 Processors CLK
100/133 MHz 2.5VMCH HCLKIN
ITP BCLK
3 APIC[0-2] APIC Bus Clock
2 Processors PICCLK
33 MHz 2.5V
ICH APICCLK
8 PCICLK[1-7,F]
PCI Bus Clock
5 PCI
Devices
CLK
33 MHz 3.3V
PCI, LPC, FWH Flash
BIOS Bus Clock
ICH PCICLK
FWH Flash BIOS
Interface Clock
FWH Flash
BIOS
CLK
LPC Interface Clock LPC CLK
4 3V66[0-3]
Hub Interface/AGP Bus
Clock
MCH CLK66
66 MHz 3.3V
Hub Interface Clock ICH CLK66
AGP Bus Clock
AGP device/
slot
CLK
Unused N/A N/A
2REF[0-1]
Internal ICH Logic ICH CLK14
14 MHz 3.3V
Internal Super I/O Logic Super I/O
Vendor
Specific
1 48 MHz USB ICH CLK48 48 MHz 3.3V
2 CPU_DIV2[0-1]
DRCG Reference Clock DRCG REFCLK
50/66 MHz 2.5V
Unused N/A N/A