User's Manual

Clocking
4-2 Intel
®
820 Chipset Design Guide
•
The MCH hub interface/AGP clock and the ICH hub interface clock.
The DRCG reference clock operates at one-half the CPU clock frequency. It is an input into the
DRCG and is used to generate the Direct RDRAM “Clock to Master” differential pair (CTM,
CTM#).
The DRCG generates one pair of differential Direct RDRAM Clocks (CTM, CTM#) from the
reference clock generated by the CK133. In addition, the DRCG uses phase information provided
by the MCH to phase align the direct RDRAM clock with the CPU clocks. This phase alignment
information is provided to the DRCG via the SYNCLKN and PCLKM pins.
Figure 4-1. Intel
®
820 Chipset Platform Clock Distribution
CPUCLK
APIC
PCICLK*
REF
48Hz
Processor
CLK
PICCLK
Processor
CLK
PICCLK
CPUCLK
APIC
MCH
CPUCLK
HCLKIN
3V66
CLK66
RDRAM RDRAMRDRAM
CTM
CFM
RCLK
TCLK
RCLKRCLK TCLK TCLK
PHASEINFO
PHASEINFO
DRCG
TERM
ICH
APIC
CPU_DIV2
REFCLK
3V66
CLK
AGP
CONNECTOR
APICCLK
PCICLK
3V66
CLK66
CLK14
CLK48
FWH
Flash BIOS
PCICLK
CLK
CLK
LPC
PCICLK
P
M
N
E
D
C
B
A
H
G
F
J
I
K
PCI SLOTS
PCI SLOTS
PCI SLOTS
PCICLK
CLK
CLK
CLK
L
L
L
CK133
Q
PCI SLOTS
CLK
L
RDRAM
RCLK
TCLK
* The free-running PCI clock should be connected to the ICH.