User's Manual

System Manufacturing
5-2 Intel
®
820 Chipset Design Guide
5.3.2 PCB Materials
PCB tolerances determine Z
0
variation. Those tolerances include trace width, pre-preg thickness,
plating thickness, and dielectric constant. Pre-preg type impacts H tolerance and ε
r
including single
ply, 2-ply, and resin content.
To design to the correct Z
0
variation, PCB’s typically need to meet the following (see Table 5-2):
•
Height tolerance ±10% (~ 0.4 mil)
•
Width tolerance ±2.5% (~ 0.4 mil)
•
ε
r
tolerance ±5% (~0.2)
Stackup Requirement: 28Ω ±10%
5.3.3 Design Process
To meet the tight tolerances required a good design process to use is:
•
Specify the material to be used
•
Calculate board geometries for the desired impedance - or use the example stackup provided
•
Build test boards and coupons
•
Measure board impedance using a TDR and follow Intel’s Impedance Test Methodology
Document (found on developer.intel.com)
•
Measure geometries with cross-section
•
Adjust design parameters and/or material as required
•
Build a new board, re-measure the key parameters and be prepared to generate one or two
board iterations
This process will require iteration: design, build, test, modify, build, test…
Figure 5-1. 28Ω Trace Geometry
H
W
S
T
ε
εε
ε