User's Manual
11-29-1999_14:46
CLOCK SYNTHESIZER
7
MULT1_GPIO11,14
4PF
C80
CK133_XIN
SIO_14MHZ_R
IHC_14MHZ_R
IHC_48MHZ_R
TEST_CLK66_R
ICH_CLK66_R
MCH_CLK66_R
SIO_PCLK7_R
FWHPCLK_R
PCLK5_R
PCLK4_R
PCLK3_R
PCLK2_R
PCLK1_R
ICHPCLK_R
ITPCLK_R
CPU_DIV2_2_R
CK133_XOUT
4,6,9 SEL133/100#
VCC_3_3_CK133_FB
PCISTOP#
CPUSTOP#
CK133_PWRDWN#
SPREAD#
SEL1
SEL0
VCC2_5_CK133_FB
PICCLK_R
33
R211
PCLK5
18
MULT1
R161
10K
10K
R206
10K
R203
JP15
9
HCLKOUT
9
RCLKOUT
22
PCLK1
14.318MHZ
Y3
21
22
R188
33
R165
33
R169
33
R186
33
R191
33
R183
23
PCLK3
23
PCLK4
12
FWHPCLK
11
ICH_14MHZ
R147
22
14
SIO_PCLK7
30
R166
AGPCLK_CONN
21
R195
33
9
MCH_CLK66
22
R221
R200
51-1%51-1%
R185
11
ICH_48MHZ
R217
10K
33
R194
JP14
10K
R202
11
MULT0_GPIO
JP17
R196
10K
R192
10K
22
R184
22
R189
33
R201
33
R187
FBHS01L
L20
21
L21
FBHS01L
12
FBHS01L
L22
12
22
R155
4
PICCLK
33
R220
11
ICH_CLK66
TEST_CLK66
R150
22
10
ICHPCLK
22
PCLK2
DRCG_CLK
DRCG_CLKB#
U12
21
17
2
12
11
24
23
22
20
18
16
15
14
10
7
6
9
8
5
4
3
1
13
R205
39-1%
R182
39-1%
VCC3_3_DRCG_FB
CLKTM_RD
0.1UF
C207
0.1UF
C215 C223
0.1UF
0.1UF
C186
0.1UF
C198
0.1UF
C206
0.1UF
C214
10PF
C185
10PF
C189
0.1UF
C199
0.1UF
C192
0.1UF
C190
0.1UF
C180
0.1UF
C208 C204
0.1UF
0.1UF
C220
10UF
C209
0.1UF
C196
10UF
C171
10UF
C170
0.1UF
C205
33
R210
14
SIO_14MHZ
R199
10K
R224
220
R197
10K
STOPB#
U11
5
55
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
4
3
2
1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
56
10K
R219
10K
R204
MULT0
DRCG_PWRDWN#
R156
22
CPU_DIV2_1_R
R148
22
4
ITPCLK
33
R164
CPU_DIV2
4,6
CPUHCLK
R170
22
8
MCHCLK
CPUHCLK1_R
CPUHCLK_R
6
CPUHCLK1
APICCLK_R
PICCLK1_R
APICCLK
10
PICCLK1
6
R151
22
CLKTM
13
13
CLKTM#
JP13
3
2
1
DRCG_CTRL11
JP11
JP18
1
2
3
PCD PLATFORM DESIGN
REV:
DRAWN BY:
LAST REVISED:
PROJECT:
SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87654321
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C
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TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD
3.03
OF 38
R
VCC3_3
VCC3_3
XTAL
VCC3_3
VCC3_3
VCC2_5
VCC3_3
VCC2_5
DRCG
GND
VDDIR
VDDP
GNDP
GNDI
GNDC
VDDC
PCLKM
VDDIPD
MULT1
MULT0
VDDO1
CLKB#
CLK
VDDO2
S1
S0
STOPB#
PWRDN#
REFCLK
GNDO1
GNDO2
SYNCLKN
19
NC
VCC3_3
VCC1_8
VCC1_8
2_5V
CK133
VDD25V_1
APIC1
APIC0
VSS7
VDD25V_2
CPU_DIV2_1
CPU_DIV2_2
VSS8
VDD25V_3
CPUCLK3
CPUCLK2
VSS9
VDD25V_4
CPUCLK1
CPUCLK0
VSS10
VDD3V_6
VSS11
CPUSTOP#
PWRDWN#
SPREAD#
SEL1
SEL0
VDD3V_7
VSS1
REF0
REF1
VDD3V_1
XTAL_OUT
VSS2
PCICLK_F
PCICLK1
VDD3V_2
PCICLK2
PCICLK3
VSS3
PCICLK4
PCICLK5
VDD3V_3
PCICLK6
PCICLK7
VSS4
VSS5
3V66_0
3V66_1
VDD3V_4
VSS6
3V66_2
3V66_3
VDD3V_5
VSS12
48MHZ
APIC2
XTAL_IN
SEL133/100#
PCISTOP#
No stuff C80
No stuff R161, JP11.
CLKTM and CLKTM# RC network must use 5% or better tolerance components.
All jumpers may not be required, but are included for test purposes.
No stuff R106
for debug.
Provide at least one 0.1uF decoupling cap per power pin.
JP13 is for debug only.
VDDIR pin on DRCG should be decoupled at the component with a 0.1uF cap.
Tie CPUCLK and MCHCLK outputs together.
Clock Synthesizer
Keep stubs on unused outputs as short as possible.
HOST
BUS/RAMBUS JP13 JP18
100/300 2-3 OUT
100/400 OUT OUT
133/400 2-3 OUT
GPO CNTRL* 1-2 OUT
Sprd Spect JP14
Enabled* IN
Disabled OUT
SEL133/100# JP15 JP17 Function
0 IN IN All outputs Tri-State
0 IN OUT Reserved
0 OUT IN Active 100MHz, 48MHz PLL inactive
0 OUT OUT Active 100MHz, 48MHz PLL active
1 IN IN Test Mode
1 IN OUT Reserved
1 OUT IN Active 133MHz,48MHz PLL inactive
1 OUT OUT Active 133MHz,48MHz PLL active*