User's Manual

11-29-1999_14:46
FWH
12
8.2K
R303
FGPI0
FGPI1
R307
15K
R304
15K
TBLK_LCK
11,14
LFRAME#/FWH4
11,14
LAD3/FWH3
LAD2/FWH2
11,14
LAD1/FWH1
11,14
LAD0/FWH0
11,14
8,10,13,14,18,21,22,23,24
PCIRST#
7
FWHPCLK
WPROT
4,6,10,34
HINIT#
R299
0K
JP21
4.7K
R308
8.2K
R298
R296
8.2K
VPP_R
FGPI3
FGPI2
FGPI4
FWH_IC
U16
18
17
16
15
7
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
2120
19
14
13
12
11
10
9
2
8
6
5
4
3
1
C300
0.1UF
C305
0.1UF
C301
0.1UF
C298
0.1UF 0.1UF
C297
0.1UF
C308
0K
R306
24 S66DETECT
24 P66DETECT 0K
R305
4.7K
R310
8.2K
R300
PCD PLATFORM DESIGN
REV:
DRAWN BY:
LAST REVISED:
PROJECT:
SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87654321
A
B
C
D
12345678
D
C
B
A
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD
3.03
OF 38
R
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
NC1
NC3
NC4
NC5
NC6
NC8
IC
CLK
VCC10
VPP
RST#
NC13
NC14
WP#
TBL# ID3
ID2
ID1
ID0
FWH0
FWH1
FWH2
FWH3
GND29
GND30
VCC31
RFU32
RFU33
RFU34
RFU35
RFU36
INIT#
FWH4
VCCA
GNDA
FGPI4
FGPI3
FGPI2
FGPI1
FGPI0
FWH
Top Block Lock
to VCC3_3 for onboard programming.
Do not tie Vpp to 12V. Vpp should be tied
For host side detection, stuff R304,R305,R306,R307.
For drive side detection, stuff R304,R307. No stuff R305,R306.
FWH
FWH JP21
OUT Locked
IN Unlocked*