User's Manual

11-29-1999_14:46 14
SUPER I/O
KBCLK
28
11
LPC_PME#
U17
27
18
45
44
15
11
10
93 65 53
96
85
14
83
9
67
77
30
95
84
98
87
92
90
16
17
78
75
74
73
72
71
70
69
6829
3
58
59
26
24
25
23
22
21
20
56
57
63
62
61
66
13
12
49
48
52
51
50
47
46
43
42
41
39
38
37
36
35
34
33
32
76 60 31
7
28
54
55
81
100
89
97
86
4
5
2
1
8
94
91
99
88
19
6
79
40
82
80
64
R312
4.7K
J20
2827
25 26
9
87
65
43
2423
2221
20
2
19
1817
1615
1413
1211
10
1
SIO_14MHZ
7
11,12,14
LAD3/FWH3
11,12,14
LAD1/FWH1
11,12,14
LAD0/FWH0
11,14
LDRQ#0
SIO_PCLK7
7,14
28
MDAT
MCLK
28
27
RXD0
27
TXD0
27
DSR#0
27
RTS#0
27
CTS#0
27
DTR#0
27
RI#0
27
DCD#0
27
RXD1
27
DSR#1
27
RTS#1
27
CTS#1
27
DTR#1
27
RI#1
27
DCD#1
28
MTR#0
28
DIR#
28
HDSEL#
28
INDEX#
28
TRK#0
26
SLIN#
28
RDATA#
26
PAR_INIT#
28
DSKCHG#
26
AFD#
26
STB#
26
SLCT
26
PE
26
BUSY
26
ACK#
26
ERR#
10,34
KBRST#
10,34
A20GATE
SERIRQ
10,14,23,34
20
PWM1
29
MIDI_IN
29
MIDI_OUT
29
J1BUTTON1
29
J1BUTTON2
29
J2BUTTON1
29
J2BUTTON2
29
JOY1X
29
JOY1Y
29
JOY2X
29
JOY2Y
11,12,14
LAD2/FWH2
28
KBDAT
27
TXD1
20
PWM2
28
DRVDEN#0
20
KEYLOCK#
28
DRVDEN#1
28
DS#0
28
STEP#
28
WDATA#
28
WGATE#
28
WRTPRT#
11,12,14 LAD3/FWH3
11,12,14 LAD2/FWH2
11,12,14 LAD1/FWH1
11,12,14 LAD0/FWH0
11,12,14 LFRAME#/FWH4
8,10,12,13,14,18,21,22,23,24PCIRST#
7,14 SIO_PCLK7
11,14 LDRQ#0
10,14,23,34 SERIRQ
PDR7
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
26
PDR[7:0]
20
IRRX
20
IRTX
8,10,12,13,14,18,21,22,23,24
PCIRST#
7,11 MULT1_GPIO
LPCPD#
SYSOPT
11,12,14
LFRAME#/FWH4
470PF
C320
470PF
C317
0.1UF
C309
0.1UF
C321C348
0.1UF
C313
0.1UF 0.1UF
C323
2.2UF
C349
21
28 VCC5_KBMS_J
4.7K
R315
RP5 4.7K
1 2 3 45
6 7 8
CPU_TACH1
4.7K
R313
11
LPC_SMI#
CPU_TACH2
4.7K
R157
PCD PLATFORM DESIGN
REV:
DRAWN BY:
LAST REVISED:
PROJECT:
SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87654321
A
B
C
D
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D
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TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD
3.03
OF 38
R
VCC3_3
SIO
LPC47B27X
A20GATE
ACK#
ALF#
AVSS
BUSY
CLKI32
CLOCKI
CTS1#
CTS2#
DCD1#
DCD2#
DIR#
DRVDEN0
DRVDEN1
DS0#
DSKCHG#
DSR1#
DSR2#
DTR1#
DTR2#
ERROR#
FAN1/GP33
FAN2/GP32
FDC_PP/DDRC/GP43
GND1 GND2 GND3 GND4
GP10/J1B1
GP11/J1B2
GP12/J2B1
GP13/J2B2
GP14/J1X
GP15/J1Y
GP16/J2X
GP17/J2Y
GP20/P17
GP21/P16
GP22/P12
GP25/MIDI_IN
GP26/MIDI_OUT
GP27/IO_SMI#
GP30/FAN_TACH2
GP31/FAN_TACH1
GP60/LED1
GP61/LED2
HDSEL#
INDEX#
INIT#
IRRX2/GP34
IRTX2/GP35
KBDRST
KCLK
KDAT
LAD0
LAD1
LAD2
LAD3
LDRQ#
LFRAME#
LRESET#
MCLK
MDAT
MTR0#
PCI_CLK PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE
PME#
RDATA#
RI1#
RI2#
RTS1#
RTS2#
RXD1
RXD2_IRRX
SERIRQ
SLCT#
SLCTIN#
STEP#
STROBE#
TRK0#
TXD1
TXD2_IRTX
VCC1 VCC2 VCC3
WDATA#
WGATE#
WRTPRT#
VREF
GP24/SYSOPT
VTR
LPCPD#
SERIAL PORT 1
SERIAL PORT 2
FDC I/F
LPC I/F
INFRARED I/F
CLOCKS
KYBD/MSE I/F
PARALLEL PORT I/F
VCC3_3
VCC5
VCC5 VCC3_3
VCC3_3
+
VCC3_3
Pulldown on SYSOPT for IO address of 0x02E
LPC header. For debug only.
Super I/O
Place decoupling caps near each power pin.Place next to VREF.