User's Manual

11-29-1999_14:46
POWER CONNECTOR
33
RSTBTN_SW
JP12
U26
SN74LVC08A
2
1
3
7
14
6
SLOTOCC1#
30 VRM1_PWRGD
U23
14
7
89
U23
56
7
14
U23
14
7
21
U23
34
7
14
RS_SCH
U20
7
14
3 4 9,11,18,31PWROK
0K
R339
R342
0K
1M
R288
R251
22K
11,31 SLP_S3#
R347 4.7K
SLP_S3
R343
22
PWRGOOD
4,6
330
R96
1M
R348
ATX_PWOK
POK_U1 POK_U2
POK_U3
RSMRST#
11,19
RSMRSTRSMRST_U
ATX_PWOK_R
PWROK_INV
U15
34
7
14
U20
21
14
7
U15
14
7
65
U15
98
7
14
U20
65
14
7
4
DBRESET#
10UF
C328C335
0.01UF
1UF
C266
U15
14
7
21
J24
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
U3
2
1
3
7
14
SW2
VRM_PWRGD30
U18
7
14
8
10
9
R349
4.7K
U9
SN74LVC08A
14
7
3
1
2
4
SLOTOCC0#
U9
14
7
8
9
10
220K
R372
U22
2
1
3
7
14
PCD PLATFORM DESIGN
REV:
DRAWN BY:
LAST REVISED:
PROJECT:
SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87654321
A
B
C
D
12345678
D
C
B
A
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD
3.03
OF 38
R
VCC3_3SBY
VCC3_3SBY
74LVC14A
VCC3_3SBY
74LVC14A
VCC3_3SBY
VCC5SBY
74LVC14A74LVC14A
VCC3_3SBYVCC3_3SBY
VCC3_3SBY
VCC3_3SBY
VCC3_3SBY
SN74LVC06A
GND
VCC
VCC3_3SBY
VCC3_3SBY
VCC3_3SBY VCC3_3SBY
VCC5M
VCC12-
VCC12
VCC5
VCC5SBY
VCC3_3
VCC5SBY
VCC2_5
VCC5SBY
VCC3_3SBY
74LVC14A
SN74LVC06A
GND
VCC
VCC3_3SBY
74LVC14A 74LVC14A
VCC3_3SBY
SN74LVC06A
GND
VCC
74LVC14A
ATX
3_3V11
-12V
GND13
PS_0N
GND15
GND16
GND17
-5V
5V19
5V20
3_3V1
3_3V2
GND3
5V4
GND5
5V6
GND7
PW_OK
5VSB
12V
SN74LVC08A
74LS132
VCC
GND
SN74LVC08A
VCC3_3SBY
VCC3_3SBY
74LVC32
330 ohm pullup to VCC3_3 located on CPU sheet.
For test only
and Schmitt trigger logic.
using a 22 msec delay
Resume Reset circuitry
No stuff.
For test only
No stuff.
ATX Connector
74LVC14A has 5V input tolerance.
ITP Reset circuit. For debug only.
SN74LVC06A has 5V input tolerance.
SN74LVC06A has 5V output tolerance.
No stuff R342 when ITP is used.
Power Connector
Reset Button
220 ohm pullup to VCC3_3 is located on VRM sheet.