User's Manual

Intel
®
820 Chipset Design Guide 2-39
Layout/Routing Guidelines
2.7.8 V
REF
Generation for AGP 2.0 (2X and 4X)
V
REF
generation for AGP 2.0 will be different depending on the AGP card type used. The 3.3V
AGP cards generate V
REF
locally (i.e., they have a resistor divider on the card that divides VDDQ
down to V
REF
) as shown in Figure 2-32. To account for potential differences between VDDQ and
GND at the MCH and graphics controller, 1.5V cards use source generated V
REF
(i.e., the V
REF
signal is generated at the graphics controller and sent to the MCH, and another V
REF
is generated at
the MCH and sent to the graphics controller). Refer to Figure 2-32.
Both the graphics controller and the MCH are required to generate V
REF
and distribute it through
the connector (1.5V add-in cards only). There are two pins defined on the AGP 2.0 universal
connector to allow this V
REF
passing. These pins are:
•
V
REF
GC - Vref from the graphics controller to the chipset
•
V
REF
CG - Vref from the chipset to the graphics controller
To preserve the common mode relationship between the V
REF
and data signals, it is important the
routing of the two Vref signals must be matched in length to the strobe lines within 0.5 inches on
the motherboard and within 0.25 inches on the add-in card.
The voltage divider networks consists of AC and DC elements as shown in the figure.
The V
REF
divider network should be placed as close to the AGP interface as is practical to get the
benefit of the common mode power supply effects. However, the trace spacing around the V
REF
signals must be a minimum of 25 mils to reduce cross-talk and maintain signal integrity.
Figure 2-31. AGP VDDQ Generation Example Circuit
SHDN IPOS
VIN INEG
GND GATE
FB COMP
C1
1 K
Ω
47 uF
10 pF
7.5 K
Ω
C2
5
Ω
R3
R4
C3
O
O
O
+12V
+3.3V
VDDQ
R1
1 uF
TYPEDET#
U1
LT1575
1
2
3
4
5
6
7
8
C5
R5
C4
R2
301
Ω
1.21 K
Ω
47 uF
220 uF
agp vddq generation vsd