User's Manual

Layout/Routing Guidelines
2-50 Intel
®
820 Chipset Design Guide
CMOS Signals
A20M# 150 Ω pull up to Vcc2.5, connect to ICH Connect to 2
nd
processor
FERR# 150 Ω pull up to Vcc2.5, connect to ICH Connect to 2
nd
processor
FLUSH# 150 Ω pull up to Vcc2.5 (not used by chipset). Connect to 2
nd
processor
IERR#
150 Ω pull up to Vcc2.5 if tied to custom logic
or leave as N/C (not used by chipset).
Connect to 2
nd
processor
IGNNE# 150 Ω pull up to Vcc2.5, connect to ICH Connect to 2
nd
processor
INIT#
150 Ω pull up to Vcc2.5, connect to ICH and
FWH Flash BIOS
Connect to 2
nd
processor
LINT0/INTR 150 Ω pull up to Vcc2.5, connect to ICH Connect to 2
nd
processor
LINT1/NMI 150 Ω pull up to Vcc2.5, connect to ICH Connect to 2
nd
processor
PICD[1:0] 150 Ω pull up to Vcc2.5, connect to ICH
Two 300–330 Ω pull ups to Vcc2.5 located
at each end of trace. Connect to 2
nd
processor
PREQ#
~200–330 Ω pull up to Vcc2.5, connect to ITP
pin 16
~200–330 Ω pull up to Vcc2.5, connect to
ITP pin 20
PWRGOOD
150–330 Ω pull up to 2.5V, output from the
PWRGOOD logic
Connect to 2
nd
processor
SLP# 150 Ω pull up to Vcc2.5, connect to ICH
SMI# 150 Ω pull up to Vcc2.5, connect to ICH
STPCLK# 150 Ω pull up to Vcc2.5, connect to ICH
THERMTRIP#
150 Ω pull up to Vcc2.5 and connect to power
off logic or ASIC, or leave as N/C
Connect to 2
nd
processor. Could tie
separately to a monitoring ASIC.
TAP Signals
PRDY#
150 Ω pull up to V
TT
, 240 Ω series resistor to
ITP pin 18
150 Ω pull up to V
TT
, 240 Ω series resistor
to ITP pin 22
TCK
1k Ω pull up to Vcc2.5, 47 Ω series resistor to
ITP pin 5
Each processor should receive a
separately buffered copy of TCK from the
ITP. Tank circuit is optional for signal
integrity. See
TDO
150 Ω pull up to Vcc2.5 and connect to ITP
10
TDO of CPU1 is connected to the ITP TDO
pin 10. Pull up both sets of TDI/TDO nets
as described.
TDI
~150–330 Ω pull up to Vcc2.5 and connect to
ITP pin 8
TDI of CPU0 is connected to the ITP pin 8,
TDI of CPU1 is connected to TDO of
CPU0. Pull up both sets of TDI/TDO nets
as described.
TMS
1KΩ pull up to Vcc2.5, 47 Ω series resistor
to ITP pin 7
Each processor should receive a
separately buffered copy of TMS from the
ITP.
Tank circuit is optional for signal integrity.
See
TRST# ~680 Ω pull down, connect to ITP pin 12 Connect to 2
nd
processor
Table 2-13. Processor and 82820 MCH Connection Checklist
1,2
(Continued)
CPU Pin UP Pin Connection (CPU0) DP Pin Connection (CPU1)