User's Manual

Layout/Routing Guidelines
2-52 Intel
®
820 Chipset Design Guide
2.12 Additional Host Bus Guidelines
BREQ Pins
UP Systems: For uni-processor systems, the BREQ0 pin should be pulled down to ground through
a 10 Ω resistor. The BREQ1 pin should be left as a no-connect.
Figure 2-41. TCK/TMS Implementation Example for DP Designs
Table 2-14. Bus Request Connection Scheme for DP Intel
®
820 Chipset Designs
Bus Signal Agent 0 Pins Agent 1 Pins
BREQ0# BR0# BR1#
BREQ1# BR1# BR0#
TCK
or
TMS
ITP Port
Vcc2.5
1 K
Ω
R
I
100 nH
100 nH
56 pF
56 pF
SC242
Connector A
SC242
Connector B
itp vsd
non-inverting buffer
non-inverting buffer
motherboard trace
motherboard trace
Figure 2-42. Single Processor BREQ Strapping Requirements
CPU #1
BREQ0# BREQ1#
No Connect