User's Manual

Layout/Routing Guidelines
2-58 Intel
®
820 Chipset Design Guide
Device-Side Detection (BIOS Queries IDE Drive for Cable Type)
Device side detection requires only a 0.047 uF capacitor on the motherboard as shown in
Figure 2-47. This mechanism creates a resistor-capacitor (RC) time constant. The ATA mode 3 or 4
drive will drive PDIAG/CBLID low and then release it (pulled up through a 10 KΩ resistor) The
drive will sample the PDIAG signal after releasing it. In an 80-conductor cable, PDIAG/CBLID is
not connected through and, therefore, the capacitor has no effect. In a 40-conductor cable, PDIAG/
CBLID is connected though to the drive. Therefore, the signal rises more slowly. The drive can
detect the difference in rise times and it reports the cable type to the BIOS when it sends the
IDENTIFY_DEVICE packet during system boot as described in the ATA/66 specification.
Layout for BOTH Host-Side and Drive-Side Cable Detection
It is possible to layout for both Host-Side and Drive-Side cable detection and decide the method to
be used during assembly. Figure 2-48 shows the layout that allows for both host-side and drive-side
detection.
•
For Host-Side Detection:
—R1 is a 0Ω resistor
—R2 is a 15KΩ resistor
— C1 is not stuffed
•
For Drive-Side Detection:
— R1 is not stuffed
— R2 is not stuffed
— C1 is a 0.047 uF capacitor
Figure 2-47. Drive-Side IDE Cable Detection
40-Conductor
Cable
IDE Drive
10 K
Ω
5V
PDIAG
ICH
0.047 uF
IDE Drive
10 K
Ω
5V
PDIAG
ICH
Open
0.047 uF
80-Conductor
IDE Cable