Manual

3-12 Chapter 3: BIOS setup
DRAM REF Cycle Time [Auto]

[48 DRAM Clock] [60 DRAM Clock] [72 DRAM Clock] [82 DRAM Clock]
[88 DRAM Clock] [90 DRAM Clock] [100 DRAM Clock] [110 DRAM Clock]
DRAM WRITE Recovery Time [Auto]

DRAM READ to PRE Time [Auto]

DRAM FOUR ACT WIN Time [Auto]

2nd Information: 1N-49-52
The values vary depending on your settings of the following sub-items:
DRAM Timing Mode [Auto]

DRAM Round Trip Latency on CHA/B [Auto]
[Auto] [Advance 15 Clock]–[Advance 1 Clock] [Normal] [Delay 1 Clock]
[Delay 15 Clock]
3rd Information: 6-6-13-9-9-9-7-6-4-7-7-4
The values vary depending on your settings of the following sub-items:
DRAM WRITE to READ Delay(DD) [Auto]

DRAM WRITE to READ Delay(DR) [Auto]

DRAM WRITE to READ Delay(SR) [Auto]

DRAM READ to WRITE Delay(DD) [Auto]

DRAM READ to WRITE Delay(DR) [Auto]

DRAM READ to WRITE Delay(SR) [Auto]

DRAM READ to READ Delay(DD) [Auto]
