User Manual
Table Of Contents
- Safety information
- Chapter 1: Product Introduction
- Chapter 2: Hardware Information
- Chapter 3: Powering Up
- Chapter 4: BIOS Setup
- 4.1 Managing and updating your BIOS
- 4.2 BIOS setup program
- 4.3 Main menu
- 4.4 Advanced menu
- 4.4.1 CPU Configuration
- 4.4.2 Power & Performance
- 4.4.3 Server ME Configuration
- 4.4.4 System Event Log
- 4.4.5 Trusted Computing
- 4.4.6 Redfish Host Interface Settings
- 4.4.7 Onboard LAN Configuration
- 4.4.8 Serial Port Console Redirection
- 4.4.9 Intel TXT Information
- 4.4.10 SIO Configuration
- 4.4.11 PCI Subsystem Settings
- 4.4.12 USB Configuration
- 4.4.13 Network Stack Configuration
- 4.4.14 CSM (Compatibility Support Module)
- 4.4.15 NVMe Configuration
- 4.4.16 APM Configuration
- 4.4.17 Third-party UEFI driver configurations
- 4.5 Chipset menu
- 4.6 Security menu
- 4.7 Boot menu
- 4.8 Monitor menu
- 4.9 Tool menu
- 4.10 Event Logs menu
- 4.11 Server Mgmt menu
- 4.12 Exit menu
- Chapter 5: RAID Configuration
- Chapter 6: Driver Installation
- Appendix
ASUS P12R-M Series
4-13
Race To Halt (RTH) [Enabled]
Allows you to enable or disable Race To Halt feature. RTH dynamically increases the
CPU frequency to quickly enter the package C-State and reduce the overall power. RTH is
controlled through MSR 1FC bit 20.
Configuration options: [Disabled] [Enabled]
Intel(R) Speed Shift Technology [Native Mode]
Allows you to enable or disable Intel(R) Speed Shift Technology support. Enabling will expose
the CPPC v2 interface to allow for hardware controlled P-states.
Configuration options: [Disabled] [Native Mode] [Out of Band Mode]
Per Core P State OS control mode [Enabled]
Allows you to enable or disable Per Core P state OS control mode. Disabling will set Bit 31 =
1 command 0x06. When set the highest core request is used for all other core requests.
Configuration options: [Disabled] [Enabled]
HwP Autonomous Per Core P State [Enabled]
[Disabled] Disable Autonomous PCPS (Bit 30 = 1, command 0x11). Autonomous will
request the same value for all cores all the time.
[Enabled] Enable PCPS (default Bit 30 = 0, command 0x11).
HwP Autonomous EPP Grouping [Enabled]
[Disabled] Disable EPP grouping (default Bit 29 = 1, command 0x11). Autonomous will
not necessarily request same values for all cores with same EPP.
[Enabled] Enable EPP grouping (default Bit 29 = 1, command 0x11). Autonomous will
request the same value for all cores with same EPP.
HwP Fast MSR Support [Enabled]
Allows you to enable or disable HwP Fast MSR Support for IA32_HWP_REQUEST MSR.
Configuration options: [Disabled] [Enabled]
HDC Control [Enabled]
[Disabled] Disable HDC.
[Enabled] Can be enable by OS if OS native support available.
Turbo Mode [Enabled]
Allows you to enable or disable processor turbo mode if EMTTM is also enabled.
Configuration options: [Disabled] [Enabled]
C-States [Enabled]
Allows you to enable or disable CPU power management, this allows the CPU to enter C-state
when not it is not 100 % utilized.
Configuration options: [Disabled] [Enabled]