User Manual

18
PRIME / TUF GAMING Intel
®
500 Series BIOS Manual
DRAM RTL (CHA DIMM0 Rank0) / DRAM RTL (CHA DIMM0 Rank1) /
DRAM RTL (CHA DIMM1 Rank0) / DRAM RTL (CHA DIMM1 Rank1) /
DRAM RTL (CHB DIMM0 Rank0) / DRAM RTL (CHB DIMM0 Rank1) /
DRAM RTL (CHB DIMM1 Rank0) / DRAM RTL (CHB DIMM1 Rank1)
Conguration options: [Auto] [0] – [127]
DRAM IOL (CHA DIMM0 Rank0) / DRAM IOL (CHA DIMM0 Rank1) /
DRAM IOL (CHA DIMM1 Rank0) / DRAM IOL (CHA DIMM1 Rank1) /
DRAM IOL (CHB DIMM0 Rank0) / DRAM IOL (CHB DIMM0 Rank1) /
DRAM IOL (CHB DIMM1 Rank0) / DRAM IOL (CHB DIMM1 Rank1)
Conguration options: [Auto] [0] – [15]
CHA IO_Latency_offset / CHB IO_Latency_offset
Conguration options: [Auto] [0] – [127]
CHA RFR delay / CHB RFR delay
Conguration options: [Auto] [0] – [127]
Memory Training Algorithms
Early Command Training
Conguration options: [Auto] [Disabled] [Enabled]
SenseAmp Offset Training
Conguration options: [Disabled] [Enabled]
Early ReadMPR Timing Centering 2D
Conguration options: [Disabled] [Enabled]
Read MPR Training
Conguration options: [Disabled] [Enabled]
Receive Enable Training
Conguration options: [Disabled] [Enabled]
Jedec Write Leveling
Conguration options: [Disabled] [Enabled]
LPDDR4 Write DQ DQS Retraining
Conguration options: [Disabled] [Enabled]
Early Write Time Centering 2D
Conguration options: [Auto] [Disabled] [Enabled]
Early Read Time Centering 2D
Conguration options: [Auto] [Disabled] [Enabled]
Write Timing Centering 1D
Conguration options: [Disabled] [Enabled]
Write Voltage Centering 1D
Conguration options: [Auto] [Disabled] [Enabled]
Read Timing Centering 1D
Conguration options: [Auto] [Disabled] [Enabled]