User Manual

PRIME / TUF GAMING Intel® 500 Series BIOSマニュアル
17
DRAM WRITE to READ Delay / DRAM WRITE to READ Delay L /
DRAM WRITE to READ Delay S
設 定オプション: [Auto] [1] – [15]
DRAM CKE Minimum Pulse Width
設 定オプション: [Auto] [0] – [15]
DRAM Write Latency
設 定オプション: [Auto] [1] – [31]
Skew Control
ODT RTT WR (CHA) / ODT RTT WR (CHB)
設 定オプション: [Auto] [0 DRAM Clock] [80 DRAM Clock]
[120 DRAM Clock] [240 DRAM Clock] [255 DRAM Clock]
ODT RTT PARK (CHA) / ODT RTT NOM (CHA) / ODT RTT PARK (CHB) /
ODT RTT NOM (CHB)
設 定オプション: [Auto] [0 DRAM Clock] [34 DRAM Clock]
[40 DRAM Clock] [48 DRAM Clock] [60 DRAM Clock]
[80 DRAM Clock] [120 DRAM Clock] [240 DRAM Clock]
ODT_READ_DURATION / ODT_READ_DELAY / ODT_WRITE_DURATION /
ODT_WRITE_DELAY
設 定オプション: [Auto] [0] – [7]
Data Rising Slope / Cmd Rising Slope / Ctl Rising Slope / Clk Rising Slope /
Data Falling Slope / Cmd Falling Slope / Ctl Falling Slope / Clk Falling Slope
設 定オプション: [Auto] [0] – [15]
Data Rising Slope Offset / Cmd Rising Slope Offset /
Ctl Rising Slope Offset / Clk Rising Slope Offset /
Data Falling Slope Offset / Cmd Falling Slope Offset /
Ctl Falling Slope Offset / Clk Falling Slope Offset
設 定オプション: [Auto] [0] [1]
RTL IOL Control
DRAM RTL INIT value
設 定オプション: [Auto] [0] – [127]
DRAM IOL INIT value(CHA) / DRAM IOL INIT value(CHB)
設 定オプション: [Auto] [0] – [15]
DRAM RTL (CHA DIMM0 Rank0) / DRAM RTL (CHA DIMM0 Rank1) /
DRAM RTL (CHA DIMM1 Rank0) / DRAM RTL (CHA DIMM1 Rank1) /
DRAM RTL (CHB DIMM0 Rank0) / DRAM RTL (CHB DIMM0 Rank1) /
DRAM RTL (CHB DIMM1 Rank0) / DRAM RTL (CHB DIMM1 Rank1)
設 定オプション: [Auto] [0] – [127]
DRAM IOL (CHA DIMM0 Rank0) / DRAM IOL (CHA DIMM0 Rank1) /
DRAM IOL (CHA DIMM1 Rank0) / DRAM IOL (CHA DIMM1 Rank1) /
DRAM IOL (CHB DIMM0 Rank0) / DRAM IOL (CHB DIMM0 Rank1) /
DRAM IOL (CHB DIMM1 Rank0) / DRAM IOL (CHB DIMM1 Rank1)
設 定オプション: [Auto] [0] – [15]