User Manual

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Pro WS sTR5 Series BIOS
3D V-Cache
X 3 D クノ
設定オプシン: [Auto] [Disable] [1 stack] [2 stack] [4 stack]
Innity Fabric Frequency and Dividers
設定オプシン: [Auto] [100 MHz] - [3000 MHz]
PCIe Speed PWM Control
アイド
設定オプシン: [Auto] [Dynamic link speed determined by Power
Management functionality] [Static Target Link Speed (GEN4)] [Static
Target Link Speed (GEN5)]
CXL Common Options
CXLトするコーネントのAV Lいて認くだ
CXL Control
すべてのCXL/ 定し
設定オプシン: [Auto] [Enabled] [Disabled]
CXL Encryption
設定オプシン: [Disabled] [Enabled]
CXL SPM
CXLメをSpecial Purpose Memory(SPMて設ます
設定オプシン: [Disabled] [Enabled] [Auto]
CXL DVSEC Lock
CXL DVSECロの有効/無効を設定ます
設定オプシン: [Disabled] [Enabled] [Auto]
Temp Gen5 Advertisement
Temp Gen5 亜土パ対図代替プコルの有効/無効を設定ます
設定オプシン: [Disabled] [Enabled] [Auto]
Sync Header Bypass
設定オプシン: [Disabled] [Enabled] [Auto]
Speculative Reads to CXL
設定オプシン: [Disabled] [Enabled] [Auto]
CXL RAS
CXL Protocol Error Reporting
CXLプロコルエラー告メカニズムをしま
設定オプシン: [Disabled] [SameAsPcieAer]
[ForceAerFwFirstIfCxlPresent]
CXL Component Error Reporting
CXLコンーネントエ告メカニ 定し
設定オプシン: [OS First] [FW-First]
Error Isolation CXL.mem
設定オプシン: [Disabled] [Enabled] [Auto]