User Manual
Table Of Contents
- 1. Knowing BIOS
- 2. BIOS setup program
- 3. My Favorites
- 4. Main menu
- 5. Extreme Tweaker menu
- 6. Advanced menu
- 6.1 Platform Misc Configuration
- 6.2 CPU Configuration
- 6.3 System Agent (SA) Configuration
- 6.4 PCH Configuration
- 6.5 PCH Storage Configuration
- 6.6 PCH-FW Configuration
- 6.7 Thunderbolt(TM) Configuration
- 6.8 Trusted Computing
- 6.9 UEFI Variables Protection
- 6.10 PCI Subsystem Settings
- 6.11 USB Configuration
- 6.12 Network Stack Configuration
- 6.13 NVMe Configuration
- 6.14 HDD/SSD SMART Information
- 6.15 APM Configuration
- 6.16 Onboard Devices Configuration
- 6.17 Intel(R) Rapid Storage Technology
- 7. Monitor menu
- 8. Boot menu
- 9. Tool menu
- 10. Exit menu
- 11. Updating BIOS
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ROG Z790 Series BIOS Manual
Initial PCIE Frequency
Allows setting a different PCIE BCLK value during POST. May be useful for setting
a lower PCIE BCLK in scenarios where memory training is not stable at a higher
BCLK (a large frequency gap between BCLK Frequency and Initial frequency is not
recommended). Applies same value as BCLK Frequency if left at default. Use the <+>
and <-> keys to adjust the value. The values range from 80.000MHz to 200.000MHz
with an interval of 0.100MHz.
Configuration options: [Auto] [80.0000] - [200.00000]
PCIE/DMI Amplitude
Allows you to set the signal magnitude of the reference PCIE/DMI CLK supplied to the
processor. Higher values may improve overclocking stability.
Configuration options: [Auto] [800mV] [900mV]
PCIE/DMI Slew Rate
Allows you set the speed at which the base clock rises or falls. Set a high value for
overclocking stability.
Configuration options: [Auto] [Slow] [Fast]
PCIE/DMI Spread Spectrum
Configuration options: [Auto] [Disabled] [Enabled]
Cold Boot PCIE Frequency
Allows you to set the PCIE Frequency at cold boot. Use the <+> and <-> keys to
adjust the value. The values range from 80.000MHz to 200.000MHz with an interval
of 0.100MHz.
Configuration options: [Auto] [80.0000] - [200.00000]
This is only with regards to PCIE clk NOT BCLK.
Realtime Memory Timing
Allows you to enable or disable realtime memory timing. When set to [Enabled], the
system will allow performing realtime memory timing changes after MRC_DONE.
Configuration options: [Disabled] [Enabled]
SPD Write Disable
Allows you to enable or disable setting SPD Write Disable. For security
recommendations, SPD write disable bit must be set.
Configuration options: [TRUE] [FALSE]
PVD Ratio Threshold
For the Core Domain PLL, the threshold to switch to lower post divider is 15 by
default. You can set a value lower than 15 when pushing high BCLK so that Digitally
Controlled Oscillator (DCO) remains at reasonable frequency.
Configuration options: [Auto] [1] - [40]
SA
PLL Frequency Override
Allows you to configure Sa PLL Frequency.
Configuration options: [Auto] [3200 MHz] [1600 MHz]
BCLK TSC HW Fixup
Allows you to enable or disable BCLK TSC HW Fixup disable during TSC copy from
PMA to APIC.
Configuration options: [Enabled] [Disabled]