User Manual
Table Of Contents
- 1 Knowing BIOS
- 2 BIOS setup program
- 3 QFan Control
- 4 My Favorites
- 5 Main menu
- 6 Ai Tweaker menu
- 7 Advanced menu
- 7.1 Platform Misc Configuration
- 7.2 CPU Configuration
- 7.3 System Agent (SA) Configuration
- 7.4 PCH Configuration
- 7.5 PCH Storage Configuration
- 7.6 PCH-FW Configuration
- 7.7 Thunderbolt(TM) Configuration
- 7.8 UEFI Variables Protection
- 7.9 PCI Subsystem Settings
- 7.10 USB Configuration
- 7.11 Network Stack Configuration
- 7.12 NVMe Configuration
- 7.13 HDD/SSD SMART Information
- 7.14 APM Configuration
- 7.15 Onboard Devices Configuration
- 8 Monitor menu
- 9 Boot menu
- 10 Tool menu
- 11 Exit menu
- 12 Updating BIOS
ROG STRIX B760 Series BIOS Manual
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Tweaker’s Paradise
The sub-items in this menu allow you to set the Tweaker’s Paradise features. Use the <+>
or <-> keys to adjust the value, or key in [Auto] and press the <Enter> key to apply the
optimized setting for the sub-items below.
Realtime Memory Timing
Allows you to enable or disable realtime memory timings. When set to [Enabled], the
system will allow performing realtime memory timing changes after MRC_DONE.
Conguration options: [Disabled] [Enabled]
SPD Write Disable
Allows you to enable or disable SPD Write Disable. For security recommendations,
SPD Write Disable bit must be set. Conguration options: [TRUE] [FALSE]
PVD Ratio Threshold
Allows you to set PVD Ratio Threshold. For the Core Domain PLL, the threshold to
switch to lower post divider is 15 by default. You can set a value lower than 15 when
pushing high BCLK so that Digitally Controlled Oscillator (DCO) remains at reasonable
frequency. Conguration options: [Auto] [1] – [40]
SA PLL Frequency Override
Conguration options: [Auto] [Disabled] [Enabled]
BCLK TSC HW Fixup
Allows you to enable or disable BCLK TSC HW Fixup. BCLK TSC HW Fixup is
disabled during TSC copy form PMA to APIC. Conguration options: [Disabled]
[Enabled]
FLL OC mode
Conguration options: [Auto] [Disabled] [Normal] [Elevated] [Extreme Elevated]
UnderVolt Protection
Allows you to enable or disable UnderVolt Protection. When UnderVolt Protection
is enabled, user will not be able to program under voltage in OS runtime. It is
recommended to keep it enabled by default.
[Disabled] Disables UnderVolt Protection in Runtime.
[Enabled] Allows BIOS undervolting, but enables UnderVolt Protection in Runtime.
Core PLL Voltage
Allows you to congure the offset for the Core PLL VCC Trim. Conguration options:
[Auto] [0.90000] – [1.84500]
GT PLL Voltage
Allows you to congure the offset for the GT PLL VCC Trim. Conguration options:
[Auto] [0.90000] – [1.84500]
Ring PLL Voltage
Allows you to congure the offset for the Ring PLL VCC Trim. Conguration options:
[Auto] [0.90000] – [1.84500]
System Agent PLL Voltage
Allows you to congure the offset for the System Agent PLL VCC Trim. Conguration
options: [Auto] [0.90000] – [1.84500]