User Manual
Table Of Contents
- 1. Knowing BIOS
- 2. BIOS setup program
- 3. My Favorites
- 4. Main menu
- 5. Ai Tweaker menu
- 6. Advanced menu
- 6.1 Platform Misc Configuration
- 6.2 CPU Configuration
- 6.3 System Agent (SA) Configuration
- 6.4 PCH Configuration
- 6.5 PCH Storage Configuration
- 6.6 PCH-FW Configuration
- 6.7 Thermal Configuration
- 6.8 Thunderbolt(TM) Configuration
- 6.9 Trusted Computing
- 6.10 UEFI Variables Protection
- 6.11 PCI Subsystem Settings
- 6.12 USB Configuration
- 6.13 Network Stack Configuration
- 6.14 NVMe Configuration
- 6.15 HDD/SSD SMART Information
- 6.16 APM Configuration
- 6.17 Onboard Devices Configuration
- 6.18 Intel(R) Rapid Storage Technology
- 7. Monitor menu
- 8. Boot menu
- 9. Tool menu
- 10. Exit menu
- 11. Updating BIOS
ROG STRIX Z790 Series (Intel
®
14
th
) BIOS Manual
49
The following item appears only when Negative Ratio Offset B is set to [User Specify].
Ratio Offset
Use the <+> and <-> keys to adjust the value.
Configuration options: [0] - [31]
The following item appears only when Overclocking TVB is set to [Boost Until Target].
Max Boost Target in MHz
Customize the maximum Target Frequency in MHz or leave auto for auto values
based on predictions. Use the <+> and <-> keys to adjust the value.
Configuration options: [Auto] [4000] - [7000]
Overclocking TVB Global Temperature Offset Sign
This selects if positive or negative offset is desired when anyone of the Overclocking
TVB Boost Profiles are selected.
Configuration options: [+] [-]
Overclocking TVB Global Temperature Offset Value
The desired value to offset the temperature thresholds of the Overclocking TVB Boost
Profiles by should be entered here.
Configuration options: [Auto] [0] - [100]
V/F Point Offset
Offset Mode Sign 1~11
Configuration options: [+] [-]
V/F Point 1~11 Offset
Configuration options: [Auto] [0.001] - [0.999]
Tweaker’s Paradise
Realtime Memory Timing
Allows you to enable or disable realtime memory timing. When set to [Enabled], the
system will allow performing realtime memory timing changes after MRC_DONE.
Configuration options: [Disabled] [Enabled]
SPD Write Disable
Allows you to enable or disable setting SPD Write Disable. For security
recommendations, SPD write disable bit must be set.
Configuration options: [TRUE] [FALSE]
PVD Ratio Threshold
For the Core Domain PLL, the threshold to switch to lower post divider is 15 by
default. You can set a value lower than 15 when pushing high BCLK so that Digitally
Controlled Oscillator (DCO) remains at reasonable frequency.
Configuration options: [Auto] [1] - [40]
SA
PLL Frequency Override
Allows you to configure Sa PLL Frequency.
Configuration options: [Auto] [3200 MHz] [1600 MHz]