User Manual
Table Of Contents
- Safety information
- Chapter 1: Product Introduction
- Chapter 2: Hardware Information
- 2.1 Chassis cover
- 2.2 Air ducts
- 2.3 Central Processing Unit (CPU)
- 2.4 System memory
- 2.5 Storage devices
- 2.6 Expansion slot
- 2.6.1 Installing an expansion card to the left PCIe riser card bracket
- 2.6.2 Installing an expansion card to the right PCIe riser card bracket
- 2.6.3 Installing a ASUS PIKE II card to the right PCIe riser card bracket
- 2.6.4 Installing an OCP 3.0 card to the OCP 3.0 slot
- 2.6.5 Installing an M.2 (NGFF) card
- 2.6.6 (optional) Installing the PFR module
- 2.6.7 Configuring an expansion card
- 2.7 Cable connections
- 2.8 Backplane cabling
- 2.9 Storage device configuration and cabling
- 2.10 Removable/optional components
- Chapter 3: Installation Options
- Chapter 4: Motherboard Information
- Chapter 5: BIOS Setup
- 5.1 Managing and updating your BIOS
- 5.2 BIOS setup program
- 5.3 Main menu
- 5.4 Performance Tuning menu
- 5.5 Advanced menu
- 5.5.1 Trusted Computing
- 5.5.2 PSP Firmware Versions
- 5.5.3 Redfish Host Interface Settings
- 5.5.4 APM Configuration
- 5.5.5 Onboard LAN Configuration
- 5.5.6 Serial Port Console Redirection
- 5.5.7 CPU Configuration
- 5.5.8 PCI Subsystem Settings
- 5.5.9 USB Configuration
- 5.5.10 Network Stack Configuration
- 5.5.11 CSM Configuration
- 5.5.12 NVMe Configuration
- 5.5.13 SATA Configuration
- 5.5.14 AMD Mem Configuration Status
- 5.6 Chipset menu
- 5.7 Security menu
- 5.8 Boot menu
- 5.9 Tool menu
- 5.10 Save & Exit menu
- 5.11 AMD CBS menu
- 5.12 Event Logs menu
- 5.13 Server Mgmt menu
- Chapter 6: Driver Installation
- Appendix
ASUS RS520A-E11-RS12U
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17. Smart Ride Through (SmaRT) setting (3-pin SMART_PSU1)
This jumper allows you to enable or disable the Smart Ride Through (SmaRT) function.
This feature is enabled by default. Set to pins 2-3 to disable it. When enabled, SmaRT
allows uninterrupted operation of the system during an AC loss event.
18. SLMPCIE SGPIO connector (6-1 pin SLM7_SGPIO1, SLM8_SGPIO1)
This connector is the SGPIO header for controlling the HDD LED function.